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april 2007 eb11_02.4 latticeec advanced evaluation board ?revision c user? guide
2 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide introduction the latticeec advanced evaluation board provides a convenient platform to evaluate, test, and debug designs with the support of latticeec advanced interface capabilities. the board provides easy access to pci, ddr sdram, fcdram and spi4.2 interfaces. the information in this document pertains only to boards marked as ?ev c? this marking is located on the front of the board, beneath the lattice logo. features required voltages supplied by pci or one external 5v dc supply ispvm system programming support spi3 flash device included for non-volatile con?uration storage ispdownload cable included 5v ac adapter included pci edge connector (120-pin) for 32-bit pci interface sodimm socket supporting 16-bit, 200mhz 200-pin ddr sdram onboard fcram spi4.2 interface via vhdm connectors prototyping area with access to over 150 i/o pins sma connectors included (10) for high-speed clock and data interfacing figure 1. latticeec advanced evaluation board electrical, mechanical and environmental speci?ations the nominal board dimensions are 9 inches by 4.2 inches. the environmental speci?ations are as follows: operating temperature: 0? to 55? storage temperature: -40? to 75? humidity: < 95% without condensation 5v dc input (+/- 10%) up to 4a, or 3.3v input from pci backplane
3 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide additional resources additional resources related to this board can be downloaded from the web at www .latticesemi.com/boards . click on the appropriate evaluation board, then see the blue ?esources box on the right of the screen for items such as: updated documentation, software, sample designs, ip evaluation bitstreams, and more. table 1. embedded functions the 3.3v oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs, depending on its position within the socket. the 16-pin socket will allow connection to pll clock pin f6 when the bottom of the oscillator is aligned to socket pins 8 and 9. when the top of the oscillator is aligned to socket pins 1 and 16, the clock is provided to primary clock pin af14. latticeec device this board features a latticeec fpga with a 1.2v dc core. it can accommodate all pin compatible latticeec devices in the 672-ball fpbga (1mm pitch) package. a complete description of this device can be found in the lat- ticeecp/ec family data sheet on the lattice web site at www .latticesemi.com . note: the connection tables listed in this document refer to the lfec20e device. available i/os and associated sysio banks may differ for other densities within this device family. programming headers two programming headers are provided on the evaluation board, providing access to the latticeec jtag port or the spi flash device. the pinouts for the headers are provided in table 2. table 2. jtag programming headers a jumper installed on jp7 provides a connection between the con?uration clock (cclk) and a general-purpose i/o. jp7 must be installed to program the spi serial flash through the latticeec device using jtag; the jumper must be removed to con?ure the latticeec device from spi flash (see the section in this document entitled spi flash download via jtag). this evaluation board utilizes dout as the gpio. when designing your own board choose the pin that is listed in lattice technical note tn1078, spi serial flash programming using ispjtag on lat- ticeecp/ec fpgas for your particular density and package description source latticeec pin notes 33.33mhz clock on-board oscillator f6 / af14 3.3v ttl output function jp6 (1x10) jp8 (2x5) vcc (3.3v) 1 6 tdo 2 7 tdi / sflash_d 3 5 ispen_n / sflash_s_n 4 10 done 5 9 tms 6 3 tck / sflash_c 8 1 initn 10 8 gnd 7, 9 2, 4 note: when using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (v cc ).
4 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide power setup for stand-alone board operation (i.e. outside of a pci backplane), the evaluation board may be supplied with a sin- gle 5v dc power supply. on-board regulators will provide the supply voltages necessary for each component. the adjustable voltage supply (v ccadj ) is set by the potentiometer located at r32 within the approximate range of 1.22v to 3.26v. the 5v dc power may be applied using the power jack at j22 or the banana jacks at j21 (5v dc) and j20 (gnd). the requirements for power jack j22 are listed in table 3. table 3. power jack j22 speci?ations power may also be supplied directly for each individual supply rail using banana jack connectors. to enable this mode of operation, the appropriate fuses must be removed. all power sources must be regulated to the speci?a- tions in table 4. no special power sequencing is required for the evaluation board. table 4. individual control of supplies when the evaluation board is inserted into a pci backplane, all onboard power will be derived from the pci 3.3v power rail. the onboard 3.3v regulator (u5) will then be automatically be disabled, allowing power to be supplied directly from the pci host system. jumper j32 allows the adjustment of the 2.5v power supply for 2.6v operation. this may be necessary for compat- ibility with high-speed ddr memory modules. a jumper in position 1-2 provides a nominal 2.5v supply. to increase the voltage to 2.6v, place the jumper in position 2-3. jumpers jp2, jp3, jp4, and jp5 allow the user to select the voltage (v ccio ) applied to the eight i/o banks of the fpga, as shown in table 5. note: care must be exercised to insure that only one voltage is strapped to each bank and certain restrictions apply depending on which features of the board are being used. polarity positive center inside diameter 0.1 (2.5mm) outside diameter 0.218 (5.5mm) current capacity 4a supply jack fuse requirement 3.3v j18 f3 (1.5a) +/- 0.3v 2.5v / 2.6v j16 f1 (3a) +/- 10% 1.2v j17 f2 (3a) +/- 5% vcc_adj j19 f4 (1.5a) user-de?ed
5 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide table 5. v ccio selection jumper depending on the optional devices installed, some sysio banks may have restrictions. table 6. sysio bank considerations the following tables detail the various standards supported by the latticeec fpga input/output (sysio) struc- tures. more information can be found in lattice technical note number tn1056, latticeecp/ec sysio usage guide , available on the lattice web site at www .latticesemi.com . table 7. mixed voltage support for example, if v ccio is connected to 3.3v, the input threshold for any pin within that sysio bank may be con?ured as 1.2v, 2.5v or 3.3v. outputs are driven to the levels present on v ccio. jp2 jp3 jp4 jp5 3.3v 1.2v 2.5v / 2.6v adjustable vccio 0 (bank0) o o o o o o o o vccio 1 o o o o o o o o vccio 2 o o o o o o o o vccio 3 o o o o o o o o vccio 4 o o o o o o o o vccio 5 o o o o o o o o vccio 6 o o o o o o o o vccio 7 (bank7) o o o o o o o o note: shown with factory default settings. bank setting 0 2.5v only (fcram interface) 1 2.5v/2.6v if ddr sdram installed in socket j11 2 2.5v if spi4.2 interface used 3 2.5v if spi4.2 interface used, 3.3v if spi3 con?uration mode used 1 . 4 3.3v when pci interface used 5 3.3v when pci interface used 6 any 7 any 1. the latticeec advanced evaluation board connects 2.5v to the v ccio of bank 3 to maxi- mize functionality of the board with the spi4.2 interface in the same bank as the syscon- fig port. for optimum sysio compatibility, 3.3v v ccio is recommended for the sysconfig port when interfacing to spi3 flash memory devices. v ccio input sysio standards output sysio standards 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v 1.5v 1.8v 2.5v 3.3v 1.2v ye s ye s ye s ye s 1.5v ye s ye s ye s ye s ye s 1.8v ye s ye s ye s ye s ye s 2.5v ye s ye s ye s ye s 3.3v ye s ye s ye s ye s
6 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide table 8. sysio standards supported per bank description top side banks 0-1 right side banks 2-3 bottom side banks 4-5 left side banks 6-7 types of i/o buffers single-ended single-ended and differential single-ended single-ended and differential output standards supported lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl25 class i, ii sstl33 class i, ii hstl15 class i, iii hstl18_i, ii, iii sstl18d class i, sstl25d class i, ii sstl33d class i, ii hstl15d class i, iii, hstl18d class i, iii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl25 class i, ii sstl33 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii sstl33d class i, ii hstl15d class i, iii hstl18d class i, iii pci33 lvds lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl2 class i, ii sstl3 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii, sstl33d class i, ii hstl15d class i, iii hstl18d class i, iii pci33 lvds25e 1 lvpecl 1 blvds 1 rsds 1 lvttl lvcmos33 lvcmos25 lvcmos18 lvcmos15 lvcmos12 sstl18 class i sstl2 class i, ii sstl3 class i, ii hstl15 class i, iii hstl18 class i, ii, iii sstl18d class i, sstl25d class i, ii, sstl33d_i, ii hstl15d class i, iii hstl18d class i, iii pci33 lvds lvds25e 1 lvpecl 1 blvds 1 rsds 1 inputs all single-ended, differential all single-ended, differential all single-ended, differential all single-ended, differential clock inputs all single-ended, differential all single-ended, differential all single-ended, differential all single-ended, differential pci support pci33 with clamp pci33 no clamp pci33 with clamp pci no clamp lvds output buffers lvds (3.5ma) buffers lvds (3.5ma) buffers 1. these differential standards are implemented by using complementary lvcmos driver with external resistor pack.
7 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide pci the latticeec evaluation board is designed to interface directly to pci 2.2 compatible systems using the pci edge connector. all necessary signals required for 32-bit pci operation are provided to the connector, as shown in tables 9 and 10. table 9. pci connections ?solder side j23 description latticeec pin sysio bank 6 pci_inta_n ab12 5 7 pci_intc_n y12 5 15 pci_rst_n ac13 5 17 pci_gnt_n ab13 4 20 pci_ad30 ad14 4 22 pci_ad28 ab14 4 23 pci_ad26 y14 4 25 pci_ad24 ae15 4 26 pci_idsel ac15 4 28 pci_ad22 aa15 4 29 pci_ad20 af16 4 31 pci_ad18 ad16 4 32 pci_ad16 ab16 4 34 pci_frame_n y16 4 36 pci_trdy_n ae17 4 38 pci_stop_n ac17 4 43 pci_par y17 4 44 pci_ad15 ae18 4 46 pci_ad13 ac18 4 47 pci_ad11 aa18 4 49 pci_ad9 af19 4 52 pci_cbe0_n aa19 4 54 pci_ad6 ae20 4 55 pci_ad4 af21 4 57 pci_ad2 af22 4 58 pci_ad0 af23 4 60 pci_req64_n aa13 4
8 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide table 10. pci connections ?component side j6 description latticeec pin sysio bank 7 pci_intb_n aa12 5 8 pci_intd_n af13 5 9 pci_prsnt1_n ae13 5 11 pci_prsnt2_n ad13 5 16 pci_clk w1 6 18 pci_req_n aa13 4 20 pci_ad31 ae14 5 21 pci_ad29 ac14 4 23 pci_ad27 aa14 4 24 pci_ad25 af15 4 26 pci_cbe3_n ad15 4 27 pci_ad23 ab15 4 29 pci_ad21 y15 4 30 pci_ad19 ae16 4 32 pci_ad17 ac16 4 33 pci_cbe2_n aa16 4 35 pci_irdy_n af17 4 37 pci_devsel_n ad17 4 40 pci_perr_n ab17 4 42 pci_serr_n aa17 4 44 pci_cbe1_n af18 4 45 pci_ad14 ad18 4 47 pci_ad12 ab18 4 48 pci_ad10 y18 4 52 pci_ad8 ae19 4 53 pci_ad7 af20 4 55 pci_ad5 aa20 4 56 pci_ad3 ae21 4 58 pci_ad1 ae22 4 60 pci_ack64_n af24 4
9 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide spi 4.2 provided for spi 4.2 interfaces are two 6x10 backplane connectors. connector j15 includes necessary data pairs and control signals for transmit data, while j14 has been con?ured for receive data. standard 100-ohm differential termination is provided for all applicable receive signal pairs. table 11. spi4.2 transmit connections j15 description latticeec pin sysio bank a1 spi4_tdat_p0 aa26 3 a2 spi4_tdat_p2 u25 3 a3 spi4_tdat_p4 t26 3 a4 spi4_tdat_p6 t21 3 a7 spi4_tdat_p8 r23 3 a8 spi4_tdat_p10 p26 3 a9 spi4_tdat_p12 p22 3 a10 spi4_tdat_p14 n22 3 b1 spi4_tdat_n0 ab26 3 b2 spi4_tdat_n2 u24 3 b3 spi4_tdat_n4 t25 3 b4 spi4_tdat_n6 u21 3 b7 spi4_tdat_n8 t24 3 b8 spi4_tdat_n10 r26 3 b9 spi4_tdat_n12 p23 3 b10 spi4_tdat_n14 n23 3 c5 spi4_tsclk ac24 3 c6 spi4_tstat0 ac26 3 c10 spi4_tctl_p n24 3 d6 spi4_tstat1 ac25 3 d10 spi4_tctl_n n25 3 e1 spi4_tdat_p1 u22 3 e2 spi4_tdat_p3 u26 3 e3 spi4_tdat_p5 t23 3 e4 spi4_tdat_p7 r22 3 e5 spi4_tdclk_p aa25 3 e7 spi4_tdat_p9 r24 3 e8 spi4_tdat_p11 p24 3 e9 spi4_tdat_p13 p21 3 e10 spi4_tdat_p15 m26 3 f1 spi4_tdat_n1 u23 3 f2 spi4_tdat_n3 v26 3 f3 spi4_tdat_n5 t22 3 f4 spi4_tdat_n7 r21 3 f5 spi4_tdclk_n ab25 3 f7 spi4_tdat_n9 r25 3 f8 spi4_tdat_n11 p25 3 f9 spi4_tdat_n13 n21 3 f10 spi4_tdat_n15 n26 3
10 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide table 12. spi4.2 receive connections j14 description latticeec pin sysio bank notes a1 spi4_rdat_p14 l21 2 100-ohm lvds termination a2 spi4_rdat_p12 l24 2 100-ohm lvds termination a3 spi4_rdat_p10 k22 2 100-ohm lvds termination a4 spi4_rdat_p8 k26 2 100-ohm lvds termination a7 spi4_rdat_p6 g25 2 100-ohm lvds termination a8 spi4_rdat_p4 h26 2 100-ohm lvds termination a9 spi4_rdat_p2 g22 2 100-ohm lvds termination a10 spi4_rdat_p0 d25 2 100-ohm lvds termination b1 spi4_rdat_n14 m21 2 100-ohm lvds termination b2 spi4_rdat_n12 l25 2 100-ohm lvds termination b3 spi4_rdat_n10 k21 2 100-ohm lvds termination b4 spi4_rdat_n8 l26 2 100-ohm lvds termination b7 spi4_rdat_n6 f25 2 100-ohm lvds termination b8 spi4_rdat_n4 j26 2 100-ohm lvds termination b9 spi4_rdat_n2 f21 2 100-ohm lvds termination b10 spi4_rdat_n0 d26 2 100-ohm lvds termination c1 spi4_rctl_p m23 2 100-ohm lvds termination c5 sp4_rstat0 c25 2 c6 spi4_rsclk d23 2 d1 spi4_rctl_n m22 2 100-ohm lvds termination d5 spi4_rstat1 c26 2 e1 spi4_rdat_p15 m24 2 100-ohm lvds termination e2 spi4_rdat_p13 l23 2 100-ohm lvds termination e3 spi4_rdat_p11 j20 2 100-ohm lvds termination e4 spi4_rdat_p9 k24 2 100-ohm lvds termination e6 spi4_rdclk_p h24 2 100-ohm lvds termination e7 spi4_rdat_p7 j25 2 100-ohm lvds termination e8 spi4_rdat_p5 j24 2 100-ohm lvds termination e9 spi4_rdat_p3 g21 2 100-ohm lvds termination e10 spi4_rdat_p1 g23 2 100-ohm lvds termination f1 spi4_rdat_n15 m25 2 100-ohm lvds termination f2 spi4_rdat_n13 l22 2 100-ohm lvds termination f3 spi4_rdat_n11 k20 2 100-ohm lvds termination f4 spi4_rdat_n9 k23 2 100-ohm lvds termination f6 spi4_rdclk_n h23 2 100-ohm lvds termination f7 spi4_rdat_n7 k25 2 100-ohm lvds termination f8 spi4_rdat_n5 h25 2 100-ohm lvds termination f9 spi4_rdat_n3 h21 2 100-ohm lvds termination f10 spi4_rdat_n1 g24 2 100-ohm lvds termination
11 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide ddr sdram the included 200-pin sodimm socket provides a built-in 16-bit interface to standard 2.5v ddr sdram memory modules. the required v ref and v tt voltages, as well as termination of each signal to v tt, are provided. table 13. ddr interface to sodimm socket j11 description latticeec pin sysio bank 5 sodimm_dq7 c15 1 6 sodimm_dq0 g14 1 7 sodimm_dq6 b16 1 8 sodimm_dq1 f14 1 11 sodimm_dqs0 g15 1 12 sodimm_dm0 f15 1 13 sodimm_dq3 d15 1 14 sodimm_dq4 e14 1 17 sodimm_dq2 e15 1 18 sodimm_dq5 c14 1 19 sodimm_dq11 f17 1 20 sodimm_dq12 d16 1 23 sodimm_dq8 g16 1 24 sodimm_dq13 c16 1 25 sodimm_dqs1 a20 1 26 sodimm_dm1 e16 1 29 sodimm_dq10 g17 1 30 sodimm_dq15 c17 1 31 sodimm_dq9 f16 1 32 sodimm_dq14 d17 1 35 sodimm_ck0 a15 1 37 sodimm_ck0_n b15 1 95 sodimm_cke1 e17 1 96 sodimm_cke0 b17 1 99 sodimm_a12 d19 1 100 sodimm_a11 a18 1 101 sodimm_a9 e18 1 102 sodimm_a8 b18 1 105 sodimm_a7 f18 1 106 sodimm_a6 d18 1 107 sodimm_a5 f19 1 108 sodimm_a4 c18 1 109 sodimm_a3 g18 1 110 sodimm_a2 a19 1 111 sodimm_a1 g19 1 112 sodimm_a0 b19 1 115 sodimm_a10 e20 1 116 sodimm_ba1 b20 1 117 sodimm_ba0 b21 1 118 sodimm_ras_n a21 1
12 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide fcram included with the evaluation board is a 256mb (8mb x 4 x 8-bit) fcram device. all necessary voltages and signal terminations are supplied. table 14. fcram connections 119 sodimm_we_n b22 1 120 sodimm_cas_n a22 1 121 sodimm_s0_n a23 1 122 sodimm_s1_n a24 1 u1 description latticeec pin sysio bank 2 fcram_dq0 a14 0 5 fcram_dq1 b14 0 8 fcram_dq2 a13 0 11 fcram_dq3 b13 0 21 fcram_a14 a11 0 22 fcram_a13 b11 0 23 fcram_fn c11 0 24 fcram_cs_n d11 0 26 fcram_ba0 a10 0 27 fcram_ba1 b10 0 28 fcram_a10 c10 0 29 fcram_a0 d10 0 30 fcram_a1 a9 0 31 fcram_a2 b9 0 32 fcram_a3 c9 0 35 fcram_a4 g10 0 36 fcram_a5 f10 0 37 fcram_a6 e10 0 38 fcram_a7 g11 0 39 fcram_a8 f11 0 40 fcram_a9 e11 0 41 fcram_a11 g12 0 42 fcram_a12 e12 0 44 fcram_pd_n f13 0 45 fcram_clk a2 0 46 fcram_clk_n a3 0 51 fcram_dqs f12 0 56 fcram_dq4 d12 0 59 fcram_dq5 c12 0 62 fcram_dq6 b12 0 65 fcram_dq7 a12 0 table 13. ddr interface to sodimm socket (continued) j11 description latticeec pin sysio bank
13 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide proto area for general purpose i/os, numerous test points are provided for direct access. the test points are labeled accord- ing to the associated i/o pin location and are listed in table 15. table 15. latticeec pins accessible at test points switches switch 1 (sw1) on the left side of the board is an eight-switch block that is part of the prototyping area. the pull-up resistors associated with sw1 are wired to 2.5v, but any i/o voltage up to 3.3v may be used. a switch in the down position produces a low (0), the up position produces a high (1). table 16 shows the connections to the latticeec i/o pins. table 16. sw1 connections sw2 is a momentary switch that the user can de?e for any purpose, such as a global reset. sw2 is wired to i/o ball e23 (bank 4) and applies a low logic level when depressed. a4 (0) c8 (0) f7 (0) k3 (7) n6 (6) u1 1 (6) aa11 (5) ae11 (5) a5 (0) d1 2 (7) f8 (0) k4 (7) p1 1 (6) u2 (6) ab4 (6) ae12 (5) a6 (0) d2 (7) f9 (0) k5 (7) p2 (6) u3 (6) ab6 (5) ae2 (5) a7 (0) d4 (0) g1 2 (7) k6 (7) p3 (6) u4 (6) ab7 (5) ae3 (5) a8 (0) d6 (0) g2 (7) l1 (7) p4 (6) u5 (6) ab8 (5) ae5 (5) a16 (1) d7 (0) g3 (7) l2 (7) p5 (6) v1 1 (6) ab9 (5) ae6 (5) a17 (1) d8 (0) g4 (7) l3 (7) p6 (6) v2 (6) ab10 (5) ae7 (5) b1 2 (7) d9 (0) g6 (7) l4 (7) r1 1 (6) w2 (6) ab11 (5) ae8 (5) b3 (0) e1 2 (7) g7 (0) l5 (7) r2 (6) w21 (3) ac4 (6) ae9 (5) b4 (0) e2 (7) g8 (0) l6 (6) r3 (6) w22 (3) ac5 (5) af2 (6) b5 (0) e3 (7) g9 (0) l7 (6) r4 (6) y8 (5) ac6 (5) af3 (5) b6 (0) e4 (7) h1 2 (7) m1 (7) r5 (6) y9 (5) ac7 (5) af5 (5) b7 (0) e6 (0) h4 (7) m2 (7) r6 (6) y10 (5) ac8 (5) af6 (5) b8 (0) e7 (0) j1 2 (7) m3 (7) t1 1 (6) y11 (5) ac9 (5) af7 (5) c1 2 (7) e8 (0) j4 (7) m4 (7) t2 (6) aa6 (5) ac10 (5) af8 (5) c4 (0) e9 (0) j5 (7) m5 (6) t3 (6) aa7 (5) ac11 (5) af9 (5) c5 (0) f1 2 (7) j6 (7) m6 (6) t4 (6) aa8 (5) ac12 (5) af10 (5) c6 (0) f2 (7) k1 (7) n4 (6) t5 (6) aa9 (5) ac23 (3) af11 (5) c7 (0) f3 (7) k2 (7) n5 (6) t6 (6) aa10 (5) ae10 (5) af12 (5) note: sysio bank indicated in parenthesis. 1. also connected to sw1. see table 16 for details. 2. also connected to leds. see table 18 for details. switch i/o ball sysio bank sw1(1) v1 6 sw1(2) u1 6 sw1(3) t1 6 sw1(4) r1 6 sw1(5) p1 6 sw1(6) m1 7 sw1(7) l1 7 sw1(8) k1 7
14 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide sw3 is a momentary switch that, when pressed, forces the fpga to start its programming cycle. sw4, when in position 1 (up), connects the download cable to the spi flash so that the user can program the flash. when sw4 is in position 2 (down) the spi flash is connected to the latticeec fpga; pressing and releas- ing sw3 (assuming the con?uration switch, sw5, is properly set) will con?ure the fpga. the fpga may be accessed via the ispjtag, using j6, no matter which position sw4 is in. sw5 determines which type of device the fpga expects to receive programming information from and whether the fpga will be master or slave during the transfer. table 17 lists the possible con?uration modes. a switch in the down position produces a low (0), the up position produces a high (1). table 17. latticeec con?uration settings leds eight user-de?able leds are provided on the upper left side of the board above sw1. these leds are each wired to a separate general purpose i/o as de?ed in table 18. the current limiting resistors associated with these leds are wired to 2.5v but any i/o voltage up to 3.3v may be used. the led will light when its associated i/o pin is driven low. table 18. leds sw5-1 sw5-2 sw5-3 con?uration mode 0 0 0 spi3 flash 0 0 1 spix flash 1 0 0 master serial 1 0 1 slave serial 1 1 0 master parallel 1 1 1 slave parallel x x x ispjtag (always available) led i/o ball sysio bank d1 b1 7 d2 c1 7 d3 d1 7 d4 e1 7 d5 f1 7 d6 g1 7 d7 h1 7 d8 j1 7
15 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide miscellaneous ten sma connectors are provided for clocks or general purpose, user-de?able signals. the center pin is wired to an i/o pin and the outer case is soldered to ground. table 19 details to which i/o pin each sma connector is wired. table 19. sma connectors one rj-45 female connector is provided for general-purpose interfacing to the latticeec device. the connections are listed in table 20. table 20. rj-45 connections download procedures requirements: pc with ispvm system v.14.3 (or later) programming management software, installed with appropriate drivers (usb driver for usb cable, windows nt/2000/xp parallel port driver for ispdownload cable). note: an option to install these drivers is included as part of the ispvm system setup. ispdownload cable (pds4102-dl2a, hw7265-dl3a, hw-usb-1a, etc.) jtag download the latticeec device can be con?ured easily via its jtag port. the device is sram-based, so the it must remain powered on to retain its con?uration when programmed in this fashion. 1. connect the ispdownload cable to the appropriate header. jp6 is used for the 1x10 cable, while jp8 is used for the 2x5 version. location i/o ball sysio bank description j2 y1 6 gp i/o (t) j3 y2 6 gp i/o (c) j4 v6 6 pll fb t, gp i/o j5 w6 6 pll fb c, gp i/o j7 n2 7 pclkt, gp i/o j8 n1 7 pclkc, gp i/o j9 ae4 5 gp i/o (t) j10 af4 5 gp i/o (c) j12 w24 3 pll in t, gp i/o j13 w23 3 pll in c, gp i/o note: t and c can be used as a differential pair. j1 latticeec pin sysio bank description 1 aa1 6 gp i/o (t), ldqs45 2 ab1 6 gp i/o (c) 3 y4 6 gp i/o (t) 4 y3 6 gp i/o (c) 5 w4 6 gp i/o (c) 6 w3 6 gp i/o (t) 7 ab2 6 gp i/o (c) 8 ac1 6 gp i/o (t)
16 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide important note: the board must be un-powered when connecting, disconnecting, or reconnecting the isp- download cable. always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag pins. failure to follow these procedures can in result in damage to the latticeecp/ec fpga device and render the board inoperable. when using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (v cc ). 2. connect the latticeec evaluation board to an external 5v supply. 3. start the ispvm system software. 4. press the ?can button located in the toolbar. the latticeec device should be automatically detected. the resulting screen should be similar to figure 2. figure 2. ispvm system interface 5. double-click the device to open the device information dialog, as shown in figure 3. in the device information dialog, click the browse button located under ?ata file? locate the desired bitstream ?e (.bit). click ok to both dialog boxes.
17 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 3. device information dialog 6. click the green ?o button. this will begin the download process into the device. 7. upon successful download, the device will be operational. spi flash download for non-volatile storage of con?uration memory, the latticeec device features an interface compatible with low- cost spi3 flash memory devices. ispvm system has the capability to program the spi3 flash device directly. dur- ing the latticeec power-up cycle, the data stored in the spi3 flash device is automatically read into con?uration memory. 1. set switch sw5 to ?00? this enables spi3 mode by setting the cfg pins of the latticeec device. 2. set switch sw4 to position 1 (up) to enable the spi3 connections from the programming headers directly to the spi3 device. 3. connect the ispdownload cable to the appropriate header. jp6 is used for the 1x10 cable, while jp8 is used for the 2x5 version. important note: the board must be un-powered when connecting, disconnecting, or reconnecting the isp- download cable. always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag pins. failure to follow these procedures can in result in damage to the latticeecp/ec fpga device and render the board inoperable. when using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (v cc ). 4. connect the evaluation board to an external 5v supply. 5. start the ispvm system software. 6. create a new chain ?e (file->new).
18 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide 7. insert a new device into the chain (edit->add device). 8. in the resulting device information dialog, shown in figure 4, press the ?elect button. figure 4. device selector dialog 9. use the pull-down menu to in the ?evice family ?ld to choose the device ?gpa loader? press ok. the resulting dialog should resemble figure 5. figure 5. fpga loader setup 10. choose the ?lash device page and press the ?elect button. 11. select the ?pi serial flash family and choose the device spi-m25p80, as shown in figure 6. press ok. note: it may be necessary to select an alternate spi3 flash device, as the part number is subject to change.
19 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 6. spi device selection 12. choose the ?on?uration data setup page, as shown in figure 14. figure 7. con?uration data setup page 13. click the ?rowse button near the top of the window. browse to the desired bitstream (.bit) ?e, created by the lattice isplever design tool. 14. press ok to exit the fpga loader setup. 15. click the green ?o button. this will begin the download process into the flash device. 16. once the download is complete, toggle switch sw4 to position 2 to restore the spi3 flash connections to the latticeec device. 17. cycle the board power. the data should automatically transfer from the flash to the fpga.
20 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide spi flash download via jtag the latticeec device is capable of programming the spi flash device from its jtag port. 1. install a jumper on jp7. this provides the cclk to gpio connection, as described in lattice technical note tn1078, spi serial flash programming using ispjtag on latticeecp/ec fpgas . 2. ensure that sw2 is set to position 2 (down) and that sw5 is set to ?00 to select the spi con?uration mode. 3. connect the latticeec evaluation board to an external 5v supply. 4. connect the ispdownload cable to the appropriate header. jp6 is used for the 1x10 cable, while jp8 is used for the 2x5 version. note: when using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (vcc). 5. start the ispvm system software. 6. press the ?can button located in the toolbar. the latticeec device should be automatically detected. the resulting screen should appear similar to figure 8. figure 8. ispvm system interface 7. double-click the device to open the device information dialog, as shown in figure 9. in the device information dialog, set the ?evice access options setting to ?dvanced spi flash programming? the spi flash program- mer dialog should immediately appear, as shown in figure 10.
21 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 9. setting the device access options note: selection of the ?dvanced spi flash programming option allows the user to specify a data ?e other than the ispvm system default. this is necessary for the latticeec advanced evaluation board. figure 10. spi flash programmer 8. choose the ?pld or fpga device page, as shown in figure 11.
22 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 11. fpga device setup 9. click the ?rowse button to select an alternate application speci? data file. choose the ?c20_adv_revc_spi_loader.bit ?e. note: this ?e is available in the design files section of the latticeec advanced evaluation board on the lattice web site (www .latticesemi.com ). 10. select the ?on?uration data setup page, as shown in figure 12. figure 12. con?uration data setup 11. browse to the desired data ?e to program into the flash device. 12. choose the ?lash device page and press the ?elect button. 13. select the ?pi serial flash family and choose the device spi-m25p80, as shown in figure 13. press ok. note: it may be necessary to select an alternate spi flash device, as the part number is subject to change.
23 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 13. spi device selection 14. press ok to exit the fpga loader setup. 15. click the green ?o button. this will begin the download process into the flash device. 16. remove the jumper at jp7. 17. cycle the board power. the data should automatically transfer from the flash to the fpga. ordering information technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal . all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. description ordering part number china rohs environment-friendly use period (efup) latticeec20 evaluation board - advanced lfec20e-h-ev latticeecp20 evaluation board - advanced LFECP20E-H-EV date version change summary previous lattice releases. december 2006 02.2 updated pci connections ?solder side table. correction for pci_ad24: connects to ball ae15. march 2007 02.3 added ordering information section. april 2007 02.4 added important information for proper connection of ispdownload (programming) cables. 10
24 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide appendix a. schematics figure 14. evaluation board block diagram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c a g b p f 2 7 6 d r a o b n o i t a u l a v e d e c n a v d a c e e c i t t a l a 8 1 , 4 2 r e b m e v o n , y a d s e n d e w 4 0 0 2 0 k n a b 3 k n a b a g p f x r 2 . 4 i p s 6 k n a b r d d t r o p p u s x t 2 . 4 i p s m a r d s i c p t i b - 2 3 5 k n a b 7 k n a b 1 k n a b g n i p y t o t o r p 2 k n a b 4 k n a b m a r c f d n o c i m e s e c i t t a ln o i t a r o p r o c r o t c u ) 2 t e e h s ( ) 3 t e e h s ( ) 6 t e e h s ( ) 4 t e e h s (
25 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 15. 32-bit pci interface 5 5 4 4 3 3 2 2 1 1 d d c c b b a a pci_ad4 pci_ad6 pci_ad9 pci_ad11 pci_ad13 pci_ad1 8 pci_ad20 pci_ad22 pci_ad24 pci_ad26 pci_ad2 8 pci_ad30 pci_ad16 pci_ad15 pci_ad1 pci_ad3 pci_ad5 pci_ad7 pci_ad 8 pci_ad10 pci_ad12 pci_ad14 pci_ad17 pci_ad19 pci_ad21 pci_ad23 pci_ad25 pci_ad27 pci_ad29 pci_ad31 pci_ad0 pci_ad2 v 3 . 3 _ i c p pci_stop_ n pci_cbe0_ n pci_cbe1_ n pci_cbe2_ n pci_cbe3_ n pci_frame_ n pci_irdy_ n pci_req_ n pci_idsel pci_serr_ n pci_perr_ n pci_par pci_g n t_ n pci_trdy_ n pci_de v sel_ n pci_ack64_ n pci_req64_ n s m t _ i c p k c t _ i c p o d t _ i c p i d t _ i c p pci_i n tb_ n pci_i n td_ n pci_i n ta_ n pci_i n tc_ n pci_prs n t1_ n pci_prs n t2_ n pci_rst_ n n _ a t n i _ i c p n _ c t n i _ i c p n _ b t n i _ i c p n _ d t n i _ i c p n _ 1 t n s r p _ i c p n _ 2 t n s r p _ i c p n _ p o t s _ i c p n _ t s r _ i c p n _ 1 e b c _ i c p n _ 2 e b c _ i c p n _ 3 e b c _ i c p n _ 4 6 q e r _ i c p n _ 4 6 k c a _ i c p 9 1 d a _ i c p n _ l e s v e d _ i c p n _ y d r t _ i c p 0 d a _ i c p 1 d a _ i c p 2 d a _ i c p 5 d a _ i c p 6 d a _ i c p 4 d a _ i c p 7 d a _ i c p 0 1 d a _ i c p 1 1 d a _ i c p 2 1 d a _ i c p 3 1 d a _ i c p 5 1 d a _ i c p 6 1 d a _ i c p 8 1 d a _ i c p 0 2 d a _ i c p 1 2 d a _ i c p 2 2 d a _ i c p 3 2 d a _ i c p 4 2 d a _ i c p 5 2 d a _ i c p 6 2 d a _ i c p 7 2 d a _ i c p 8 2 d a _ i c p 9 2 d a _ i c p 0 3 d a _ i c p 1 3 d a _ i c p 8 d a _ i c p 9 d a _ i c p 3 d a _ i c p n _ 0 e b c _ i c p n _ e m a r f _ i c p n _ y d r i _ i c p n _ t n g _ i c p r a p _ i c p n _ r r e s _ i c p n _ r r e p _ i c p l e s d i _ i c p n _ q e r _ i c p 7 1 d a _ i c p 4 1 d a _ i c p 4 f a _ a m s 4 e a _ a m s k l c _ i c p pci_clk k l c p _ c s o pci_m66e n o i v _ i c p o i v _ i c p v 3 . 3 _ i c p k c t _ i c p o d t _ i c p s m t _ i c p i d t _ i c p 5 _ o i c c v 4 _ o i c c v 1 1 e a _ p t 2 1 c a _ p t 2 1 d a _ p t 2 1 e a _ p t 2 1 f a _ p t 1 1 f a _ p t 1 1 b a _ p t 0 1 f a _ p t 1 1 c a _ p t 8 e a _ p t 9 e a _ p t 0 1 e a _ p t 9 f a _ p t 8 f a _ p t 0 1 a a _ p t 7 d a _ p t 1 1 y _ p t 1 1 d a _ p t 0 1 b a _ p t 7 f a _ p t 6 e a _ p t 6 f a _ p t 0 1 d a _ p t 7 e a _ p t 0 1 y _ p t 5 f a _ p t 9 a a _ p t 5 e a _ p t 0 1 c a _ p t 6 d a _ p t 9 d a _ p t 3 f a _ p t 9 b a _ p t 3 e a _ p t 4 d a _ p t 5 d a _ p t 9 y _ p t 2 f a _ p t 9 c a _ p t 8 d a _ p t 8 c a _ p t 8 b a _ p t 5 c a _ p t 6 c a _ p t 8 a a _ p t 2 e a _ p t 8 y _ p t 7 c a _ p t 6 a a _ p t 6 b a _ p t 7 a a _ p t 7 b a _ p t 1 1 a a _ p t 7 5 _ d n g _ i c p k l c _ i c p k l c p _ c s o e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c i c p t i b - 2 3 c 8 2 4 0 0 2 , 4 2 r e b m e v o n , y a d s e n d e w ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 7 [ ] 7 [ ] 5 [ ] 5 [ ] 5 [ ] 5 [ ] 7 [ ] 7 [ a r o p r o c r o t c u d n o c i m e s e c i t t a ln o i t ) 4 e a ( p ) 4 f a ( n ] 6 [ ] 6 [ 5 4 1 c 5 0 8 0 f u 0 1 1 2 7 7 c f u 1 . 0 1 2 8 7 c f u 1 . 0 1 2 4 7 r k 5 6 9 c f u 1 . 0 1 2 5 8 c f u 1 . 0 1 2 6 4 1 c 5 0 8 0 f u 0 1 1 2 1 8 c f u 1 . 0 1 2 6 j e d i s t n e n o p m o c n n o c e g d e i c p -12 v 1 tck 2 gro u nd_3 3 tdo 4 +5 v _5 5 +5 v _7 6 i n tb# 7 i n td# 8 prs n t1# 9 reser v ed_10 10 prs n t2# 11 reser v ed_14 14 gro u nd_15 15 clk 16 gro u nd_17 17 req# 1 8 + v io_19 19 ad[31] 20 ad[29] 21 gro u nd_22 22 ad[27] 23 ad[25] 24 +3.3 v _25 25 c/be#[3] 26 ad[23] 27 gro u nd_2 8 2 8 ad[21] 29 ad[19] 30 +3.3 v _31 31 ad[17] 32 c/be#[2] 33 gro u nd_34 34 irdy# 35 +3.3 v _36 36 de v sel# 37 gro u nd_3 8 3 8 lock# 39 perr# 40 +3.3 v _41 41 serr# 42 +3.3 v _43 43 c/be#[1] 44 ad[14] 45 gro u nd_46 46 ad[12] 47 ad[10] 4 8 m66e n 49 ad[0 8 ] 52 ad[07] 53 +3.3 v _54 54 ad[05] 55 ad[03] 56 gro u nd_57 57 ad[01] 5 8 + v io_59 59 ack64# 60 +5 v _61 61 +5 v _62 62 4 7 c f u 1 . 0 1 2 9 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 4 8 c f u 1 . 0 1 2 3 2 j e d i s r e d l o s n n o c e g d e i c p trst# 1 +12 v 2 tms 3 tdi 4 +5 v _5 5 i n ta# 6 i n tc# 7 +5 v _ 8 8 reser v ed_9 9 + v io_10 10 reser v ed_11 11 3.3 v aux 14 rst# 15 + v io_16 16 g n t# 17 gro u nd_1 8 1 8 pme# 19 ad[30] 20 +3.3 v _21 21 ad[2 8 ] 22 ad[26] 23 gro u nd_24 24 ad[24] 25 idsel 26 +3.3 v _27 27 ad[22] 2 8 ad[20] 29 gro u nd_30 30 ad[1 8 ] 31 ad[16] 32 +3.3 v _33 33 frame# 34 gro u nd_35 35 trdy# 36 gro u nd_37 37 stop# 3 8 +3.3 v _39 39 reser v ed_40 40 reser v ed_41 41 gro u nd_42 42 par 43 ad[15] 44 +3.3 v _45 45 ad[13] 46 ad[11] 47 gro u nd_4 8 4 8 ad[09] 49 c/be#[0] 52 +3.3 v _53 53 ad[06] 54 ad[04] 55 gro u nd_56 56 ad[02] 57 ad[00] 5 8 + v io_59 59 req64# 60 +5 v _61 61 +5 v _62 62 9 9 c f u 1 . 0 1 2 9 4 1 c 1 0 . 0 1 2 ) 5 f o 2 ( 4 k n a b 5 k n a b 2 c e f l) 2 7 6 a g b p f ( e 0 b 3 u 2 7 6 - c e 0 2 c e f l a 2 b p 6 b a b 2 b p 6 a a a 3 b p 7 c a b 3 b p 8 y a 4 b p 7 b a a 5 b p 6 c a 6 s q d b / a 6 b p 8 b a a 7 b p 2 e a a 8 b p 2 f a a 9 b p 5 d a a 0 1 b p 8 d a a 1 1 b p 3 e a a 2 1 b p 3 f a a 3 1 b p 4 e a 4 1 s q d b / a 4 1 b p 5 e a a 5 1 b p 5 f a a 6 1 b p 6 d a a 7 1 b p 6 f a a 8 1 b p 7 f a a 9 1 b p 7 e a a 0 2 b p 7 d a a 1 2 b p 8 f a 2 2 s q d b / a 2 2 b p 1 1 d a a 3 2 b p 8 e a a 4 2 b p 0 1 f a a 5 2 b p 0 1 e a a 6 2 b p 1 1 a a a 7 2 b p 1 1 e a a 8 2 b p 2 1 f a a 9 2 b p 2 1 d a 0 3 s q d b / a 0 3 b p 2 1 a a a 1 3 b p 3 1 e a 5 _ 2 f e r v / a 2 3 b p 3 1 d a 0 _ 5 t k l c p / a 3 3 b p 4 1 f a b 4 b p 7 a a b 5 b p 5 c a b 6 b p 8 c a b 7 b p 8 a a b 8 b p 9 y b 9 b p 4 d a b 0 1 b p 9 c a b 1 1 b p 9 b a b 2 1 b p 9 d a b 3 1 b p 4 f a b 4 1 b p 9 a a b 5 1 b p 0 1 y b 6 1 b p 0 1 c a b 7 1 b p 6 e a b 8 1 b p 0 1 b a b 9 1 b p 0 1 d a b 0 2 b p 0 1 a a b 1 2 b p 9 f a b 2 2 b p 1 1 y b 3 2 b p 1 1 c a b 4 2 b p 1 1 b a b 5 2 b p 9 e a b 6 2 b p 2 1 y b 7 2 b p 1 1 f a b 8 2 b p 2 1 e a b 9 2 b p 2 1 c a b 0 3 b p 2 1 b a b 1 3 b p 3 1 f a 5 _ 1 f e r v / b 2 3 b p 3 1 c a 0 _ 5 c k l c p / b 3 3 b p 4 1 e a a 4 3 b p / n e t i r w 3 1 a a a 5 3 b p / 4 _ 1 f e r v 4 1 d a a 6 3 b p / 4 _ 2 f e r v 4 1 c a a 7 3 b p / 5 d 5 1 f a a 8 3 b p / 8 3 s q d b 5 1 d a a 9 3 b p 6 1 f a a 0 4 b p 6 1 e a a 1 4 b p 7 1 f a a 2 4 b p 5 1 y a 3 4 b p 7 1 d a a 4 4 b p 8 1 d a a 5 4 b p 8 1 e a a 6 4 b p / 6 4 s q d b 6 1 d a a 7 4 b p 9 1 f a a 8 4 b p 7 1 a a a 9 4 b p 1 2 f a a 0 5 b p 1 2 e a a 1 5 b p 2 2 f a a 2 5 b p 2 2 e a a 3 5 b p 9 1 e a a 4 5 b p / 4 5 s q d b 9 1 a a a 5 5 b p 3 2 f a a 6 5 b p 8 1 c a a 7 5 b p 4 2 f a b 4 3 b p / n 1 s c 3 1 b a b 5 3 b p / n s c 4 1 a a b 6 3 b p / 7 d 4 1 b a b 7 3 b p / 6 d 5 1 e a b 8 3 b p / 4 d 5 1 c a b 9 3 b p / 3 d 4 1 y b 0 4 b p / 2 d 5 1 b a b 1 4 b p / 1 d 7 1 e a b 2 4 b p 5 1 a a b 3 4 b p 6 1 y b 4 4 b p 6 1 c a b 5 4 b p 8 1 f a b 6 4 b p 6 1 b a b 7 4 b p 6 1 a a b 8 4 b p 7 1 y b 9 4 b p 0 2 f a b 0 5 b p 7 1 c a b 1 5 b p 7 1 b a b 2 5 b p 8 1 a a b 3 5 b p 0 2 e a b 4 5 b p 8 1 y b 5 5 b p 0 2 a a b 6 5 b p 8 1 b a b 7 5 b p 3 2 e a 5 o c c v 0 1 v 5 o c c v 1 1 v 5 o c c v 2 1 v 5 o c c v 2 1 w 5 o c c v 3 1 v 5 o c c v 3 1 w 4 o c c v 7 1 v 4 o c c v 6 1 v 4 o c c v 5 1 w 4 o c c v 5 1 v 4 o c c v 4 1 w 4 o c c v 4 1 v 0 1 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 7 6 c f u 1 . 0 1 2 1 3 j 3 n o c 1 2 3 3 7 c f u 1 . 0 1 2 8 8 c f u 1 . 0 1 2 2 0 1 c f u 1 . 0 1 2 3 7 r 0
26 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 16. ddr sdram and fcram 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 1 q d _ m a r c f 0 q d _ m a r c f 3 q d _ m a r c f 2 q d _ m a r c f 6 q d _ m a r c f 7 q d _ m a r c f 4 q d _ m a r c f 5 q d _ m a r c f 4 1 a _ m a r c f 3 1 a _ m a r c f 0 1 a _ m a r c f 0 a _ m a r c f 1 a _ m a r c f 2 a _ m a r c f 5 a _ m a r c f 4 a _ m a r c f 7 a _ m a r c f 6 a _ m a r c f 9 a _ m a r c f 8 a _ m a r c f 2 1 a _ m a r c f 1 1 a _ m a r c f 3 a _ m a r c f 0 a b _ m a r c f 1 a b _ m a r c f n f _ m a r c f n _ s c _ m a r c f 1 1 a _ m m i d o s 8 a _ m m i d o s 6 a _ m m i d o s 4 a _ m m i d o s 2 a _ m m i d o s 0 a _ m m i d o s 1 a _ m m i d o s 3 a _ m m i d o s 5 a _ m m i d o s 7 a _ m m i d o s 9 a _ m m i d o s 2 1 a _ m m i d o s 0 1 a _ m m i d o s 1 e k c _ m m i d o s 0 1 a _ m m i d o s 3 a _ m m i d o s 9 a _ m m i d o s 1 a _ m m i d o s 5 a _ m m i d o s 2 1 a _ r d d 9 a _ r d d 1 e k c _ r d d 7 a _ r d d 3 a _ r d d 1 a _ r d d 0 1 a _ r d d 5 a _ r d d 0 m d _ r d d 1 q d _ r d d 4 q d _ r d d 0 q d _ r d d 3 1 q d _ m m i d o s 5 1 q d _ m m i d o s 2 q d _ m m i d o s 0 s q d _ m m i d o s n _ 0 k c _ m m i d o s 8 q d _ m m i d o s 5 q d _ m m i d o s 0 k c _ m m i d o s 4 q d _ m m i d o s 1 1 q d _ m m i d o s 6 q d _ m m i d o s 9 q d _ m m i d o s 1 s q d _ m m i d o s 7 q d _ m m i d o s 0 1 q d _ m m i d o s 2 1 q d _ m m i d o s 1 m d _ m m i d o s 4 1 q d _ m m i d o s 1 q d _ m m i d o s 0 q d _ m m i d o s 3 q d _ m m i d o s 0 m d _ m m i d o s 0 a b _ m m i d o s 1 a b _ m m i d o s n _ s a r _ m m i d o s n _ s a c _ m m i d o s n _ e w _ m m i d o s n _ 0 s _ m m i d o s 0 e k c _ m m i d o s n _ 1 s _ m m i d o s 1 e k c _ m m i d o s 0 a b _ m m i d o s n _ e w _ r d d n _ 0 s _ r d d 0 a b _ r d d s q d _ m a r c f s q d _ m a r c f n _ d p _ m a r c f n _ d p _ c f s q d _ c f k l c _ m a r c f 2 1 a _ m m i d o s n _ e w _ m m i d o s 7 a _ m m i d o s v 5 . 2 _ c c v f e r v 3 q d _ r d d 6 q d _ r d d 0 s q d _ r d d 2 1 q d _ r d d 1 s q d _ r d d 1 m d _ r d d 5 1 q d _ r d d 1 1 q d _ r d d 3 1 q d _ r d d 0 1 q d _ r d d 8 q d _ r d d 7 q d _ r d d 2 a _ c f 1 a _ c f 4 a _ c f 3 a _ c f 5 a _ c f 0 a _ c f 6 a _ c f 7 a _ c f 0 1 a _ c f 9 a _ c f 8 a _ c f 1 1 a _ c f 2 1 a _ c f 3 1 a _ c f 4 1 a _ c f n f _ c f 2 1 a _ m a r c f 4 1 a _ m a r c f n f _ m a r c f 0 a _ m a r c f 1 a _ m a r c f 2 a _ m a r c f 3 a _ m a r c f 4 a _ m a r c f 5 a _ m a r c f 6 a _ m a r c f 7 a _ m a r c f 8 a _ m a r c f 9 a _ m a r c f 0 1 a _ m a r c f 1 1 a _ m a r c f n _ s c _ c f 0 a b _ c f 1 a b _ c f n _ s c _ m a r c f 0 a b _ m a r c f 1 a b _ m a r c f 3 1 a _ m a r c f 1 q d _ c f n _ 1 s _ r d d n _ s a c _ r d d 0 e k c _ r d d 0 1 a _ r d d 1 1 a _ r d d 6 q d _ r d d 3 q d _ c f 5 a _ r d d 1 1 q d _ r d d 0 s q d _ r d d n _ s c _ c f 5 a _ c f 4 1 q d _ r d d 3 1 q d _ r d d 3 q d _ r d d 2 q d _ c f 1 a _ c f 9 a _ c f n _ 0 s _ r d d 0 a _ r d d 9 q d _ r d d 7 q d _ r d d n _ d p _ m a r c f 5 q d _ c f 1 1 a _ c f 3 a _ c f 4 a _ r d d 0 1 q d _ r d d n _ d p _ c f 7 a _ c f 0 a _ c f 3 a _ r d d 0 m d _ r d d 5 q d _ r d d 4 1 a _ c f 1 a b _ c f 6 a _ c f 2 1 a _ r d d 6 a _ r d d 1 a b _ r d d n _ 0 k c _ r d d 0 q d _ r d d 0 a b _ c f n f _ c f 0 q d _ c f 2 1 a _ c f n _ e w _ r d d 1 a _ r d d 0 k c _ r d d 1 e k c _ r d d 1 m d _ r d d 7 1 a _ p t 4 q d _ c f 2 a _ c f 2 a _ r d d 8 q d _ r d d 2 q d _ r d d 1 q d _ r d d 4 a _ c f 9 a _ r d d 5 1 q d _ r d d 1 s q d _ r d d s q d _ c f 0 1 a _ c f 0 a b _ r d d n _ s a r _ r d d 4 q d _ r d d 3 1 a _ c f 7 a _ r d d 2 1 q d _ r d d 8 a _ c f 6 1 a _ p t 8 a _ r d d n _ k l c _ m a r c f f e r v f e r v n _ k l c _ c f n _ k l c _ m a r c f k l c _ m a r c f k l c _ c f f e r v f e r v 1 q d _ c f 2 q d _ c f 0 q d _ c f 3 q d _ c f 4 q d _ c f 5 q d _ c f 6 q d _ c f 7 q d _ c f 0 q d _ m a r c f 1 q d _ m a r c f 2 q d _ m a r c f 3 q d _ m a r c f 7 q d _ m a r c f 6 q d _ m a r c f 5 q d _ m a r c f 4 q d _ m a r c f 7 q d _ c f 6 q d _ c f 0 k c _ m m i d o s n _ 0 k c _ m m i d o s 0 k c _ r d d n _ 0 k c _ r d d 0 q d _ m m i d o s 0 m d _ m m i d o s t t v 1 q d _ m m i d o s 4 q d _ m m i d o s t t v 7 q d _ m m i d o s 6 q d _ m m i d o s 0 s q d _ m m i d o s 3 q d _ m m i d o s 2 q d _ m m i d o s 2 q d _ r d d 5 q d _ r d d 5 q d _ m m i d o s 4 1 q d _ r d d 9 q d _ r d d 1 1 q d _ m m i d o s 8 q d _ m m i d o s 1 s q d _ m m i d o s 0 1 q d _ m m i d o s 9 q d _ m m i d o s t t v 2 1 q d _ m m i d o s 4 1 q d _ m m i d o s 5 1 q d _ m m i d o s 3 1 q d _ m m i d o s 1 m d _ m m i d o s 1 1 a _ m m i d o s 8 a _ r d d 0 e k c _ r d d 6 a _ m m i d o s 1 a b _ r d d 2 a _ m m i d o s 0 e k c _ m m i d o s 1 1 a _ r d d 2 a _ r d d 0 a _ r d d 4 a _ r d d 0 a _ m m i d o s 4 a _ m m i d o s 8 a _ m m i d o s 6 a _ r d d 1 a b _ m m i d o s n _ s a c _ m m i d o s n _ 1 s _ m m i d o s n _ s a r _ m m i d o s n _ s a c _ r d d n _ s a r _ r d d n _ 1 s _ r d d n _ 0 s _ m m i d o s t t v t t v t t v f e r v 1 _ o i c c v v 5 . 2 _ c c v 0 _ o i c c v 8 d _ p t 8 e _ p t 4 c _ p t 8 g _ p t 7 e _ p t 7 f _ p t 9 e _ p t 8 f _ p t 7 d _ p t 7 c _ p t 5 a _ p t 5 c _ p t 4 a _ p t 8 c _ p t 9 f _ p t 7 a _ p t 9 g _ p t 9 d _ p t 6 b _ p t 6 a _ p t 4 d _ p t 7 b _ p t 3 b _ p t 8 a _ p t 6 d _ p t 6 c _ p t 6 e _ p t 7 g _ p t 4 b _ p t 8 b _ p t 5 b _ p t e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c m a r c f d n a m a r d s r d d c 8 3 4 0 0 2 , 4 2 r e b m e v o n , y a d s e n d e w ] 7 [ ] 7 [ ] 7 [ , ] 3 [ t h g i r ( f o d n e s i t t v ) d n a l s i t t v ) d n a l ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ ] 6 [ a r o p r o c r o t c u d n o c i m e s e c i t t a ln o i t f o d n e t f e l ( 2 2 c f u 1 . 0 1 2 3 8 0 x 1 4 7 s t c 2 2 8 1 n r 1 2 3 4 8 7 6 5 2 u 8 - p o s p s n 5 9 9 2 p l q d d v 5 n i v a 6 n i v p 7 f e r v 4 t t v 8 e s n e s v 3 g n d 2 9 6 c f u 1 . 0 1 2 3 6 1 x 1 4 7 s t c 5 2 4 1 n r 1 2 3 4 5 6 7 8 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 r n 15 33 cts 741x0 8 3 1 2 3 4 8 7 6 5 5 3 1 c f u 1 . 0 1 2 2 2 7 4 r 3 8 0 x 1 4 7 s t c 5 2 1 n r 1 2 3 4 8 7 6 5 0 2 1 3 4 r t n i o p t s e t 2 p t n i p 1 4 c f u 1 . 0 1 2 3 2 c f u 1 . 0 1 2 9 7 c f u 1 . 0 1 2 3 6 1 x 1 4 7 s t c 2 2 8 n r 1 2 3 4 5 6 7 8 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 3 8 0 x 1 4 7 s t c 2 2 2 2 n r 1 2 3 4 8 7 6 5 3 3 c f u 1 . 0 2 1 5 6 c f u 1 . 0 1 2 0 9 c f u 1 . 0 1 2 1 2 n r 3 8 0 x 1 4 7 s t c 3 3 1 2 3 4 8 7 6 5 9 1 c f u 1 . 0 1 2 1 u t f c 6 0 8 m l 9 5 c t a b i h s o t m a r c f 1 _ d d v 1 6 6 _ s s v 6 6 3 _ q d d v 3 0 q d 2 1 q d 5 2 q d 8 3 q d 1 1 4 q d 6 5 5 q d 9 5 6 q d 2 6 7 q d 5 6 3 1 a 2 2 4 1 a 1 2 4 _ c n 4 7 _ c n 7 0 1 _ c n 0 1 3 1 _ c n 3 1 4 1 _ c n 4 1 6 1 _ c n 6 1 7 1 _ c n 7 1 9 1 _ c n 9 1 0 2 _ c n 0 2 0 a b 6 2 1 a b 7 2 0 1 a 8 2 0 a 9 2 1 a 0 3 2 a 1 3 3 a 2 3 3 3 _ d d v 3 3 2 1 a 2 4 1 1 a 1 4 9 a 0 4 8 a 9 3 7 a 8 3 6 a 7 3 5 a 6 3 4 a 5 3 4 3 _ s s v 4 3 6 _ q s s v 6 2 1 _ q s s v 2 1 4 6 _ q s s v 4 6 8 5 _ q s s v 8 5 2 5 _ q s s v 2 5 8 4 _ s s v 8 4 3 6 _ c n 3 6 0 6 _ c n 0 6 7 5 _ c n 7 5 4 5 _ c n 4 5 3 5 _ c n 3 5 0 5 _ c n 0 5 7 4 _ c n 7 4 3 4 _ c n 3 4 5 2 _ c n 5 2 1 6 _ q d d v 1 6 5 5 _ q d d v 5 5 9 _ q d d v 9 5 1 _ q d d v 5 1 8 1 _ d d v 8 1 n f 3 2 s c / 4 2 s q d 1 5 f e r v 9 4 k l c / 6 4 k l c 5 4 d p / 4 4 6 3 1 c f u 1 . 0 1 2 6 6 c f u 1 . 0 1 2 3 8 0 x 1 4 7 s t c 2 2 0 1 n r 1 2 3 4 8 7 6 5 9 1 n r 3 6 1 x 1 4 7 s t c 3 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r44 33 r n 17 33 cts 741x0 8 3 1 2 3 4 8 7 6 5 a 1 1 j r d d v 5 . 2 t e k c o s m m i d - o s n i p - 0 0 2 f e r v 1 f e r v 2 s s v 3 s s v 4 0 q d 5 4 q d 6 1 q d 7 5 q d 8 d d v 9 d d v 0 1 0 s q d 1 1 0 m d 2 1 2 q d 3 1 6 q d 4 1 s s v 5 1 s s v 6 1 3 q d 7 1 7 q d 8 1 8 q d 9 1 2 1 q d 0 2 d d v 1 2 d d v 2 2 9 q d 3 2 3 1 q d 4 2 1 s q d 5 2 1 m d 6 2 s s v 7 2 s s v 8 2 0 1 q d 9 2 4 1 q d 0 3 1 1 q d 1 3 5 1 q d 2 3 d d v 3 3 d d v 4 3 0 k c 5 3 d d v 6 3 # 0 k c 7 3 s s v 8 3 s s v 9 3 s s v 0 4 2 2 7 1 r 3 6 c f u 1 . 0 1 2 2 2 3 1 r r12 33 t n i o p t s e t 5 p t n i p 1 5 2 1 1 r 3 8 0 x 1 4 7 s t c 2 2 4 n r 1 2 3 4 8 7 6 5 3 8 0 x 1 4 7 s t c 2 2 6 n r 1 2 3 4 8 7 6 5 3 8 0 x 1 4 7 s t c 5 2 2 1 n r 1 2 3 4 8 7 6 5 2 3 c f u 1 . 0 1 2 1 c d e z i s f u 7 4 1 2 0 1 r 0 2 1 r n 3 33 cts 741x0 8 3 1 2 3 4 8 7 6 5 3 6 1 x 1 4 7 s t c 5 2 3 1 n r 1 2 3 4 5 6 7 8 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 0 2 c f u 1 . 0 1 2 3 8 c f u 1 . 0 1 2 2 2 5 1 r 1 4 1 c 5 0 8 0 f u 0 1 1 2 3 8 0 x 1 4 7 s t c 2 2 6 1 n r 1 2 3 4 8 7 6 5 9 0 1 c f u 1 . 0 1 2 7 1 c f u 1 . 0 1 2 3 8 0 x 1 4 7 s t c 5 2 2 n r 1 2 3 4 8 7 6 5 8 9 c f u 1 . 0 1 2 2 c f u 1 . 0 1 2 b 1 1 j r d d v 5 . 2t e k c o s m m i d - o s n i p - 0 0 2 6 1 q d 1 4 0 2 q d 2 4 7 1 q d 3 4 1 2 q d 4 4 d d v 5 4 d d v 6 4 2 s q d 7 4 2 m d 8 4 8 1 q d 9 4 2 2 q d 0 5 s s v 1 5 s s v 2 5 9 1 q d 3 5 3 2 q d 4 5 4 2 q d 5 5 8 2 q d 6 5 d d v 7 5 d d v 8 5 5 2 q d 9 5 9 2 q d 0 6 3 s q d 1 6 3 m d 2 6 s s v 3 6 s s v 4 6 6 2 q d 5 6 0 3 q d 6 6 7 2 q d 7 6 1 3 q d 8 6 d d v 9 6 d d v 0 7 ) 0 b c ( 1 7 ) 4 b c ( 2 7 ) 1 b c ( 3 7 ) 5 b c ( 4 7 s s v 5 7 s s v 6 7 ) 8 s q d ( 7 7 ) 8 m d ( 8 7 ) 2 b c ( 9 7 ) 6 b c ( 0 8 d d v 1 8 d d v 2 8 ) 3 b c ( 3 8 ) 7 b c ( 4 8 5 8 _ c n 5 8 6 8 _ c n 6 8 s s v 7 8 s s v 8 8 ) 2 k c ( 9 8 s s v 0 9 ) # 2 k c ( 1 9 d d v 2 9 d d v 3 9 d d v 4 9 ) 1 e k c ( 5 9 0 e k c 6 9 7 9 _ c n 7 9 8 9 _ c n 8 9 2 1 a 9 9 1 1 a 0 0 1 9 a 1 0 1 8 a 2 0 1 s s v 3 0 1 s s v 4 0 1 7 a 5 0 1 6 a 6 0 1 5 a 7 0 1 4 a 8 0 1 3 a 9 0 1 2 a 0 1 1 1 a 1 1 1 0 a 2 1 1 d d v 3 1 1 d d v 4 1 1 0 1 a 5 1 1 1 a b 6 1 1 0 a b 7 1 1 # s a r 8 1 1 # e w 9 1 1 # s a c 0 2 1 # 0 s 1 2 1 ) # 1 s ( 2 2 1 3 2 1 _ c n 3 2 1 4 2 1 _ c n 4 2 1 s s v 5 2 1 s s v 6 2 1 2 3 q d 7 2 1 6 3 q d 8 2 1 3 3 q d 9 2 1 7 3 q d 0 3 1 d d v 1 3 1 d d v 2 3 1 4 s q d 3 3 1 4 m d 4 3 1 4 3 q d 5 3 1 8 3 q d 6 3 1 s s v 7 3 1 s s v 8 3 1 5 3 q d 9 3 1 9 3 q d 0 4 1 0 4 q d 1 4 1 4 4 q d 2 4 1 d d v 3 4 1 d d v 4 4 1 1 4 q d 5 4 1 5 4 q d 6 4 1 5 s q d 7 4 1 5 m d 8 4 1 s s v 9 4 1 s s v 0 5 1 2 4 q d 1 5 1 6 4 q d 2 5 1 3 4 q d 3 5 1 7 4 q d 4 5 1 d d v 5 5 1 d d v 6 5 1 d d v 7 5 1 ) # 1 k c ( 8 5 1 s s v 9 5 1 ) 1 k c ( 0 6 1 s s v 1 6 1 s s v 2 6 1 8 4 q d 3 6 1 2 5 q d 4 6 1 9 4 q d 5 6 1 3 5 q d 6 6 1 d d v 7 6 1 d d v 8 6 1 6 s q d 9 6 1 6 m d 0 7 1 0 5 q d 1 7 1 4 5 q d 2 7 1 s s v 3 7 1 s s v 4 7 1 1 5 q d 5 7 1 5 5 q d 6 7 1 6 5 q d 7 7 1 0 6 q d 8 7 1 d d v 9 7 1 d d v 0 8 1 7 5 q d 1 8 1 1 6 q d 2 8 1 7 s q d 3 8 1 7 m d 4 8 1 s s v 5 8 1 s s v 6 8 1 8 5 q d 7 8 1 2 6 q d 8 8 1 9 5 q d 9 8 1 3 6 q d 0 9 1 d d v 1 9 1 d d v 2 9 1 a d s 3 9 1 0 a s 4 9 1 l c s 5 9 1 1 a s 6 9 1 d p s d d v 7 9 1 2 a s 8 9 1 9 9 1 _ c n 9 9 1 ) s s v ( 0 0 2 2 2 6 1 r 8 1 c f u 1 . 0 1 2 8 6 c f u 1 . 0 1 2 3 6 1 x 1 4 7 s t c 2 2 0 2 n r 1 2 3 4 5 6 7 8 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 4 2 c f u 1 . 0 1 2 0 8 c f u 1 . 0 1 2 5 2 c d e z i s f u 0 2 2 1 2 4 3 1 c f u 1 . 0 1 2 2 2 5 4 r 2 4 1 c 5 0 8 0 f u 0 1 1 2 1 3 1 c d e z i s f u 0 2 2 1 2 r41 33 r n 5 33 cts 741x0 8 3 1 2 3 4 8 7 6 5 0 k n a b 1 k n a b ) 5 f o 4 ( 2 c e f l ) 2 7 6 a g b p f ( e 0 d 3 u 2 7 6 - c e 0 2 c e f l a 4 3 t p 4 1 c b 4 3 t p 4 1 f 1 _ 1 f e r v / a 5 3 t p 3 1 e 1 _ 2 f e r v / b 5 3 t p 4 1 d a 6 3 t p 4 1 g b 6 3 t p 4 1 e a 7 3 t p 5 1 a b 7 3 t p 5 1 b 8 3 s q d t / a 8 3 t p 5 1 g b 8 3 t p 5 1 f a 9 3 t p 5 1 c b 9 3 t p 5 1 e a 0 4 t p 6 1 b b 0 4 t p 5 1 d a 1 4 t p 6 1 a b 1 4 t p 7 1 a a 2 4 t p 8 1 b b 2 4 t p 6 1 g a 3 4 t p 8 1 a b 3 4 t p 6 1 f a 4 4 t p 6 1 c b 4 4 t p 6 1 d a 5 4 t p 9 1 b b 5 4 t p 9 1 a 6 4 s q d t / a 6 4 t p 0 2 a b 6 4 t p 6 1 e a 7 4 t p 0 2 b b 7 4 t p 7 1 g a 8 4 t p 0 2 e b 8 4 t p 7 1 f a 9 4 t p 7 1 d b 9 4 t p 7 1 c a 0 5 t p 7 1 b b 0 5 t p 7 1 e a 1 5 t p 1 2 a b 1 5 t p 8 1 g a 2 5 t p 2 2 a b 2 5 t p 8 1 f a 3 5 t p 8 1 c b 3 5 t p 8 1 d 4 5 s q d t / a 4 5 t p 1 2 b b 4 5 t p 9 1 g a 5 5 t p 2 2 b b 5 5 t p 9 1 f a 6 5 t p 9 1 d b 6 5 t p 8 1 e a 7 5 t p 3 2 a b 7 5 t p 4 2 a 0 o c c v 2 1 h 0 o c c v 3 1 h 0 o c c v 0 1 j 0 o c c v 1 1 j 0 o c c v 2 1 j 0 o c c v 3 1 j 1 o c c v 4 1 h 1 o c c v 5 1 h 1 o c c v 4 1 j 1 o c c v 5 1 j 1 o c c v 6 1 j 1 o c c v 7 1 j a 2 t p 6 e b 2 t p 7 d a 3 t p 6 d b 3 t p 7 f a 4 t p 4 d b 4 t p 7 e a 5 t p 5 c b 5 t p 4 c a 6 t p / 6 s q d t 7 g b 6 t p 8 d a 7 t p 3 b b 7 t p 8 e a 8 t p 4 b b 8 t p 8 f a 9 t p 2 a b 9 t p 3 a a 0 1 t p 5 b b 0 1 t p 8 g a 1 1 t p 8 c b 1 1 t p 9 e a 2 1 t p 6 b b 2 1 t p 9 f a 3 1 t p 4 a b 3 1 t p 5 a a 4 1 t p / 4 1 s q d t 9 d b 4 1 t p 9 g a 5 1 t p 9 c b 5 1 t p 0 1 e a 6 1 t p 6 a b 6 1 t p 0 1 f a 7 1 t p 0 1 d b 7 1 t p 0 1 c a 8 1 t p 6 c b 8 1 t p 0 1 g a 9 1 t p 7 c b 9 1 t p 1 1 g a 0 2 t p 7 a b 0 2 t p 1 1 e a 1 2 t p 7 b b 1 2 t p 8 b a 2 2 t p / 2 2 s q d t 1 1 c b 2 2 t p 1 1 d a 3 2 t p 8 a b 3 2 t p 1 1 f a 4 2 t p 9 b b 4 2 t p 2 1 e a 5 2 t p 9 a b 5 2 t p 2 1 g a 6 2 t p 0 1 a b 6 2 t p 0 1 b a 7 2 t p 2 1 c b 7 2 t p 2 1 d a 8 2 t p 1 1 b b 8 2 t p 1 1 a a 9 2 t p 2 1 b b 9 2 t p 2 1 a a 0 3 t p / 0 3 s q d t 2 1 f b 0 3 t p 3 1 f a 1 3 t p 3 1 b b 1 3 t p 3 1 a a 2 3 t p / 0 _ 2 f e r v 3 1 c b 2 3 t p / 0 _ 1 f e r v 3 1 d a 3 3 t p / 0 _ 0 t k l c p 4 1 a b 3 3 t p / 0 _ 0 c k l c p 4 1 b r14 33 9 r k 0 1 9 n r 3 6 1 x 1 4 7 s t c 3 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 3 c f u 1 . 0 1 2 6 1 c f u 1 . 0 1 2 0 2 1 6 4 r 1 2 c f u 1 . 0 1 2 4 5 c f u 1 . 0 1 2 7 8 c f u 1 . 0 1 2 7 n r 3 8 0 x 1 4 7 s t c 3 3 1 2 3 4 8 7 6 5 1 9 c f u 1 . 0 1 2 6 7 c f u 1 . 0 1 2
27 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 17. spi 4.2 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 8 n _ t a d r _ 4 i p s 3 1 n _ t a d r _ 4 i p s i p s i s 0 1 p _ t a d r _ 4 i p s 1 t a t s r _ 4 i p s 4 p _ t a d r _ 4 i p s 3 1 p _ t a d r _ 4 i p s n i p s s c 9 n _ t a d r _ 4 i p s n _ l t c r _ 4 i p s 0 n _ t a d r _ 4 i p s 2 p _ t a d r _ 4 i p s 4 1 n _ t a d r _ 4 i p s 2 1 p _ t a d r _ 4 i p s 3 p _ t a d r _ 4 i p s 7 n _ t a d r _ 4 i p s 5 1 n _ t a d r _ 4 i p s 0 t a t s r _ 4 i p s 5 p _ t a d r _ 4 i p s k l c s r _ 4 i p s p _ l t c t _ 4 i p s n _ l t c t _ 4 i p s 4 1 p _ t a d t _ 4 i p s 4 1 n _ t a d t _ 4 i p s 1 p _ t a d r _ 4 i p s 1 n _ t a d r _ 4 i p s 2 n _ t a d r _ 4 i p s 3 n _ t a d r _ 4 i p s 9 p _ t a d r _ 4 i p s 1 1 n _ t a d r _ 4 i p s 0 1 n _ t a d r _ 4 i p s 5 n _ t a d r _ 4 i p s 4 n _ t a d r _ 4 i p s 7 p _ t a d r _ 4 i p s 2 1 n _ t a d r _ 4 i p s 5 1 p _ t a d r _ 4 i p s p _ l t c r _ 4 i p s 3 1 p _ t a d t _ 4 i p s 3 1 n _ t a d t _ 4 i p s 5 1 p _ t a d t _ 4 i p s 5 1 n _ t a d t _ 4 i p s 2 1 p _ t a d t _ 4 i p s 2 1 n _ t a d t _ 4 i p s 1 1 p _ t a d t _ 4 i p s 1 1 n _ t a d t _ 4 i p s 7 p _ t a d t _ 4 i p s 7 n _ t a d t _ 4 i p s 0 1 p _ t a d t _ 4 i p s 0 1 n _ t a d t _ 4 i p s 9 p _ t a d t _ 4 i p s 9 n _ t a d t _ 4 i p s 8 p _ t a d t _ 4 i p s 8 n _ t a d t _ 4 i p s 5 p _ t a d t _ 4 i p s 5 n _ t a d t _ 4 i p s 4 p _ t a d t _ 4 i p s 4 n _ t a d t _ 4 i p s 6 p _ t a d t _ 4 i p s 6 n _ t a d t _ 4 i p s 1 p _ t a d t _ 4 i p s 3 p _ t a d t _ 4 i p s 1 n _ t a d t _ 4 i p s 3 n _ t a d t _ 4 i p s 2 p _ t a d t _ 4 i p s 2 n _ t a d t _ 4 i p s 0 p _ t a d t _ 4 i p s 0 n _ t a d t _ 4 i p s p _ k l c d t _ 4 i p s n _ k l c d t _ 4 i p s k l c s t _ 4 i p s 0 t a t s t _ 4 i p s 1 t a t s t _ 4 i p s 0 d i p s 1 2 w _ p t 2 2 w _ p t 6 2 y _ p t 3 2 c a _ p t 6 n _ t a d r _ 4 i p s p _ k l c d r _ 4 i p s n _ k l c d r _ 4 i p s n r s g 3 2 e _ p t 0 n _ t a d t _ 4 i p s 0 n _ t a d r 2 n _ t a d t _ 4 i p s 2 n _ t a d r 4 n _ t a d t _ 4 i p s 4 n _ t a d r 6 n _ t a d t _ 4 i p s 6 n _ t a d r 8 n _ t a d t _ 4 i p s 8 n _ t a d r 0 1 n _ t a d t _ 4 i p s 0 1 n _ t a d r 2 1 n _ t a d t _ 4 i p s 2 1 n _ t a d r 4 1 n _ t a d t _ 4 i p s 4 1 n _ t a d r 6 p _ t a d t _ 4 i p s 6 p _ t a d r 4 p _ t a d t _ 4 i p s 4 p _ t a d r 0 p _ t a d t _ 4 i p s 0 p _ t a d r 2 p _ t a d t _ 4 i p s 2 p _ t a d r k l c s t _ 4 i p s k l c s r 0 t a t s t _ 4 i p s 0 t a t s r p _ l t c t _ 4 i p s p _ l t c r 1 t a t s t _ 4 i p s 1 t a t s r n _ l t c t _ 4 i p s n _ l t c r 1 p _ t a d t _ 4 i p s 1 p _ t a d r 3 p _ t a d t _ 4 i p s 3 p _ t a d r 5 p _ t a d t _ 4 i p s 5 p _ t a d r 7 p _ t a d t _ 4 i p s 7 p _ t a d r p _ k l c d t _ 4 i p s p _ k l c d r 9 p _ t a d t _ 4 i p s 9 p _ t a d r 1 1 p _ t a d t _ 4 i p s 1 1 p _ t a d r 3 1 p _ t a d t _ 4 i p s 3 1 p _ t a d r 5 1 p _ t a d t _ 4 i p s 5 1 p _ t a d r 1 n _ t a d t _ 4 i p s 1 n _ t a d r 3 n _ t a d t _ 4 i p s 3 n _ t a d r 5 n _ t a d t _ 4 i p s 5 n _ t a d r 7 n _ t a d t _ 4 i p s 7 n _ t a d r n _ k l c d t _ 4 i p s n _ k l c d r 9 n _ t a d t _ 4 i p s 9 n _ t a d r 1 1 n _ t a d t _ 4 i p s 1 1 n _ t a d r 3 1 n _ t a d t _ 4 i p s 3 1 n _ t a d r 5 1 n _ t a d t _ 4 i p s 5 1 n _ t a d r 2 1 p _ t a d t _ 4 i p s 2 1 p _ t a d r 0 1 p _ t a d t _ 4 i p s 0 1 p _ t a d r 8 p _ t a d t _ 4 i p s 8 p _ t a d r 4 1 p _ t a d t _ 4 i p s 4 1 p _ t a d r 3 2 w _ a m s 4 2 w _ a m s p _ l t c t p _ l t c r _ 4 i p s 0 t a t s t 0 t a t s r _ 4 i p s k l c s t k l c s r _ 4 i p s n _ l t c t n _ l t c r _ 4 i p s 1 t a t s t 1 t a t s r _ 4 i p s 5 1 p _ t a d t 5 1 p _ t a d r _ 4 i p s 3 1 p _ t a d t 3 1 p _ t a d r _ 4 i p s 9 p _ t a d t 9 p _ t a d r _ 4 i p s p _ k l c d t p _ k l c d r _ 4 i p s 7 p _ t a d t 7 p _ t a d r _ 4 i p s 5 p _ t a d t 5 p _ t a d r _ 4 i p s 3 p _ t a d t 3 p _ t a d r _ 4 i p s 1 p _ t a d t 1 p _ t a d r _ 4 i p s 5 1 n _ t a d t 5 1 n _ t a d r _ 4 i p s 3 1 n _ t a d t 3 1 n _ t a d r _ 4 i p s 1 1 n _ t a d t 1 1 n _ t a d r _ 4 i p s 9 n _ t a d t 9 n _ t a d r _ 4 i p s n _ k l c d t n _ k l c d r _ 4 i p s 7 n _ t a d t 7 n _ t a d r _ 4 i p s 5 n _ t a d t 5 n _ t a d r _ 4 i p s 3 n _ t a d t 3 n _ t a d r _ 4 i p s 1 n _ t a d t 1 n _ t a d r _ 4 i p s 1 1 p _ t a d r _ 4 i p s 1 1 p _ t a d t 1 1 p _ t a d r _ 4 i p s 2 1 n _ t a d t 2 1 n _ t a d r _ 4 i p s 6 p _ t a d t 6 p _ t a d r _ 4 i p s 0 p _ t a d t 0 p _ t a d r _ 4 i p s 0 1 p _ t a d t 0 1 p _ t a d r _ 4 i p s 2 1 p _ t a d t 2 1 p _ t a d r _ 4 i p s 4 1 p _ t a d t 4 1 p _ t a d r _ 4 i p s 6 p _ t a d r _ 4 i p s 4 n _ t a d t 4 n _ t a d r _ 4 i p s 0 p _ t a d r _ 4 i p s 8 p _ t a d r _ 4 i p s 2 n _ t a d t 2 n _ t a d r _ 4 i p s 4 1 p _ t a d r _ 4 i p s 6 n _ t a d t 6 n _ t a d r _ 4 i p s 8 n _ t a d t 8 n _ t a d r _ 4 i p s 2 p _ t a d t 2 p _ t a d r _ 4 i p s 0 n _ t a d t 0 n _ t a d r _ 4 i p s 4 p _ t a d t 4 p _ t a d r _ 4 i p s 0 1 n _ t a d t 0 1 n _ t a d r _ 4 i p s 4 1 n _ t a d t 4 1 n _ t a d r _ 4 i p s 8 p _ t a d t 8 p _ t a d r _ 4 i p s i p s i s 0 d i p s 2 _ o i c c v 3 _ o i c c v n i p s s c n r s g 6 2 y _ p t e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c 2 . 4 i p s c 8 4 4 0 0 2 , 4 2 r e b m e v o n , y a d s e n d e w ] 7 [ ] 7 [ ] 5 [ ] 5 [ ] 5 [ a r o p r o c r o t c u d n o c i m e s e c i t t a ln o i t ] 5 [ ] 5 [ ) 3 2 w ( n ) 4 2 w ( p n o t n i r p t o o f 4 1 je d i s r e d l o s n o t n i r p t o o f 5 1 je d i s r e d l o s a g p f c e e c i t t a l o t m o r fa g p f c e e c i t t a l 3 f 6 e 5 j 3 a 7 e 7 d 4 e 0 1 l 7 a 5 c 1 j 8 k 1 l 0 1 b 6 a 8 h 3 e 9 e 5 b 9 k 7 j 9 c 4 b 4 a 3 l 2 d 9 l 6 c 4 g 4 j 3 k 7 b 8 b 2 g 1 c 1 a 6 b 9 j 6 k 6 f 8 j 2 e 2 c 8 g 6 l 8 d 2 j 0 1 c 9 f 8 e 0 1 d 0 1 f 1 e 8 c 5 a 9 a 0 1 a 3 d 3 j 2 k 5 f 5 e 1 k 0 1 e 5 l 7 g 9 d 7 k 1 g 9 b 3 c 4 l 2 a 8 a 5 g 0 1 h 0 1 g 7 h 8 l 4 f 7 f 7 l 6 j 1 d 8 f 1 f 5 k 3 h 4 c 1 b 2 h 3 g 1 h 5 d 4 k 0 1 k 2 f 4 d 3 b 4 h 6 h 6 g 2 b 2 l 6 d 7 c 9 g 5 h 9 h 0 1 j 3 f 6 e 5 j 3 a 7 e 7 d 4 e 0 1 l 7 a 5 c 1 j 8 k 1 l 0 1 b 6 a 8 h 3 e 9 e 5 b 9 k 7 j 9 c 4 b 4 a 3 l 2 d 9 l 6 c 4 g 4 j 3 k 7 b 8 b 2 g 1 c 1 a 6 b 9 j 6 k 6 f 8 j 2 e 2 c 8 g 6 l 8 d 2 j 0 1 c 9 f 8 e 0 1 d 0 1 f 1 e 8 c 5 a 9 a 0 1 a 3 d 3 j 2 k 5 f 5 e 1 k 0 1 e 5 l 7 g 9 d 7 k 1 g 9 b 3 c 4 l 2 a 8 a 5 g 0 1 h 0 1 g 7 h 8 l 4 f 7 f 7 l 6 j 1 d 8 f 1 f 5 k 3 h 4 c 1 b 2 h 3 g 1 h 5 d 4 k 0 1 k 2 f 4 d 3 b 6 h 4 h 6 g 2 b 2 l 6 d 7 c 9 g 5 h 9 h 0 1 j t n i o p t s e t 6 p t n i p 1 0 0 1 9 4 r 0 0 1 1 6 r 4 2 1 c f u 1 . 0 1 2 0 0 1 3 5 r 0 0 1 5 5 r 2 2 1 c f u 1 . 0 1 2 3 4 1 c 5 0 8 0 f u 0 1 1 2 3 9 c f u 1 . 0 1 2 2 k n a b ) 5 f o 3 ( 3 k n a b 2 c e f l ) 2 7 6 a g b p f ( e 0 c 3 u 2 7 6 - c e 0 2 c e f l a 2 r p / 2 _ 2 f e r v 3 2 d b 2 r p / 2 _ 1 f e r v 3 2 e a 5 r p 2 2 g b 5 r p 1 2 f a 6 r p / 6 s q d r 5 2 d b 6 r p 6 2 d a 7 r p 1 2 g b 7 r p 1 2 h a 8 r p / a _ n i _ t l l p _ 0 m u r 4 2 h b 8 r p / a _ n i _ c l l p _ 0 m u r 3 2 h a 9 r p / a _ b f _ t l l p _ 0 m u r 5 2 g b 9 r p / a _ b f _ c l l p _ 0 m u r 5 2 f a 1 1 r p 4 2 k b 1 1 r p 3 2 k a 3 r p 5 2 c b 3 r p 6 2 c a 4 r p 3 2 g b 4 r p 4 2 g a 2 1 r p 0 2 j b 2 1 r p 0 2 k a 3 1 r p 2 2 k b 3 1 r p 1 2 k a 4 1 r p 4 2 j b 4 1 r p 5 2 h a 5 1 r p 6 2 h b 5 1 r p 6 2 j a 6 1 r p 5 2 j b 6 1 r p 5 2 k a 7 1 r p 4 2 l b 7 1 r p 5 2 l a 8 1 r p 3 2 l b 8 1 r p 2 2 l a 9 1 r p / 9 1 s q d r 1 2 l b 9 1 r p 1 2 m a 0 2 r p 4 2 m b 0 2 r p 5 2 m a 1 2 r p 3 2 m b 1 2 r p 2 2 m a 2 2 r p / 0 _ 2 t k l c p 6 2 k b 2 2 r p / 0 _ 2 c k l c p 6 2 l a 4 2 r p 4 2 n b 4 2 r p 5 2 n a 5 2 r p 2 2 n b 5 2 r p 3 2 n a 6 2 r p 1 2 p b 6 2 r p 1 2 n a 7 2 r p 6 2 m b 7 2 r p 6 2 n 8 2 s q d r / a 8 2 r p 2 2 p b 8 2 r p 3 2 p a 9 2 r p 4 2 p b 9 2 r p 5 2 p a 0 3 r p 2 2 r b 0 3 r p 1 2 r a 1 3 r p 6 2 p b 1 3 r p 6 2 r a 2 3 r p 4 2 r b 2 3 r p 5 2 r a 3 3 r p 3 2 r b 3 3 r p 4 2 t a 4 3 r p 3 2 t b 4 3 r p 2 2 t a 5 3 r p 6 2 t b 5 3 r p 5 2 t 6 3 s q d r / a 6 3 r p 1 2 t b 6 3 r p 1 2 u a 7 3 r p 2 2 u b 7 3 r p 3 2 u a 8 3 r p 5 2 u b 8 3 r p 4 2 u a 9 3 r p 6 2 u b 9 3 r p 6 2 v 0 d i p s / 7 d / a 1 4 r p 6 2 w i p s i s / y s u b / b 1 4 r p 5 2 w b o s c / t u o d / a 2 4 r p 6 2 y n i p s s c / i d / b 2 4 r p 5 2 y a _ b f _ t l l p _ 0 m l r / a 3 4 r p 1 2 w a _ b f _ c l l p _ 0 m l r / b 3 4 r p 2 2 w a _ n i _ t l l p _ 0 m l r / a 4 4 r p 4 2 w a _ n i _ c l l p _ 0 m l r / b 4 4 r p 3 2 w 5 4 s q d r / a 5 4 r p 6 2 a a b 5 4 r p 6 2 b a a 6 4 r p 5 2 a a b 6 4 r p 5 2 b a a 7 4 r p 6 2 c a b 7 4 r p 5 2 c a 3 _ 1 f e r v / a 8 4 r p 4 2 c a 3 _ 2 f e r v / b 8 4 r p 3 2 c a 2 o c c v 7 1 k 2 o c c v 8 1 k 2 o c c v 8 1 l 2 o c c v 8 1 m 2 o c c v 8 1 n 2 o c c v 9 1 n 3 o c c v 8 1 p 3 o c c v 9 1 p 3 o c c v 8 1 r 3 o c c v 9 1 r 3 o c c v 8 1 t 3 o c c v 8 1 u 4 9 c f u 1 . 0 1 2 2 1 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 0 0 1 9 5 r t n i o p t s e t 4 p t n i p 1 4 4 1 c 5 0 8 0 f u 0 1 1 2 0 0 1 8 5 r 3 2 1 c f u 1 . 0 1 2 2 1 1 c f u 1 . 0 1 2 0 2 1 c f u 1 . 0 1 2 0 0 1 9 1 r 0 0 1 0 6 r 1 1 1 c f u 1 . 0 1 2 3 1 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 0 0 1 0 2 r 0 0 1 8 4 r t n i o p t s e t 3 p t n i p 1 4 1 j 2 0 0 1 - 7 5 0 4 7 m d h v x e l o m 1 a 1 a 2 a 2 a 3 a 3 a 4 a 4 a 5 a 5 a 6 a 6 a 7 a 7 a 8 a 8 a 9 a 9 a 0 1 a 0 1 a 1 b 1 b 2 b 2 b 3 b 3 b 4 b 4 b 5 b 5 b 6 b 6 b 7 b 7 b 8 b 8 b 9 b 9 b 0 1 b 0 1 b 1 c 1 c 2 c 2 c 3 c 3 c 4 c 4 c 5 c 5 c 6 c 6 c 7 c 7 c 8 c 8 c 9 c 9 c 0 1 c 0 1 c 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 d 9 d 9 d 0 1 d 0 1 d 1 e 1 e 2 e 2 e 3 e 3 e 4 e 4 e 5 e 5 e 6 e 6 e 7 e 7 e 8 e 8 e 9 e 9 e 0 1 e 0 1 e 1 f 1 f 2 f 2 f 3 f 3 f 4 f 4 f 5 f 5 f 6 f 6 f 7 f 7 f 8 f 8 f 9 f 9 f 0 1 f 0 1 f 1 g _ d n g 1 g 2 g _ d n g 2 g 3 g _ d n g 3 g 4 g _ d n g 4 g 5 g _ d n g 5 g 6 g _ d n g 6 g 7 g _ d n g 7 g 8 g _ d n g 8 g 9 g _ d n g 9 g 0 1 g _ d n g 0 1 g 1 h _ d n g 1 h 2 h _ d n g 2 h 3 h _ d n g 3 h 4 h _ d n g 4 h 5 h _ d n g 5 h 6 h _ d n g 6 h 7 h _ d n g 7 h 8 h _ d n g 8 h 9 h _ d n g 9 h 0 1 h _ d n g 0 1 h 1 j _ d n g 1 j 2 j _ d n g 2 j 3 j _ d n g 3 j 4 j _ d n g 4 j 5 j _ d n g 5 j 6 j _ d n g 6 j 7 j _ d n g 7 j 8 j _ d n g 8 j 9 j _ d n g 9 j 0 1 j _ d n g 0 1 j 1 k _ d n g 1 k 2 k _ d n g 2 k 3 k _ d n g 3 k 4 k _ d n g 4 k 5 k _ d n g 5 k 6 k _ d n g 6 k 7 k _ d n g 7 k 8 k _ d n g 8 k 9 k _ d n g 9 k 0 1 k _ d n g 0 1 k 1 l _ d n g 1 l 2 l _ d n g 2 l 3 l _ d n g 3 l 4 l _ d n g 4 l 5 l _ d n g 5 l 6 l _ d n g 6 l 7 l _ d n g 7 l 8 l _ d n g 8 l 9 l _ d n g 9 l 0 1 l _ d n g 0 1 l 0 0 1 4 5 r 0 0 1 7 5 r 6 2 1 c f u 1 . 0 1 2 0 0 1 6 5 r 0 0 1 0 5 r 0 0 1 1 5 r 5 1 j 2 0 0 1 - 7 5 0 4 7 m d h v x e l o m 1 a 1 a 2 a 2 a 3 a 3 a 4 a 4 a 5 a 5 a 6 a 6 a 7 a 7 a 8 a 8 a 9 a 9 a 0 1 a 0 1 a 1 b 1 b 2 b 2 b 3 b 3 b 4 b 4 b 5 b 5 b 6 b 6 b 7 b 7 b 8 b 8 b 9 b 9 b 0 1 b 0 1 b 1 c 1 c 2 c 2 c 3 c 3 c 4 c 4 c 5 c 5 c 6 c 6 c 7 c 7 c 8 c 8 c 9 c 9 c 0 1 c 0 1 c 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 d 9 d 9 d 0 1 d 0 1 d 1 e 1 e 2 e 2 e 3 e 3 e 4 e 4 e 5 e 5 e 6 e 6 e 7 e 7 e 8 e 8 e 9 e 9 e 0 1 e 0 1 e 1 f 1 f 2 f 2 f 3 f 3 f 4 f 4 f 5 f 5 f 6 f 6 f 7 f 7 f 8 f 8 f 9 f 9 f 0 1 f 0 1 f 1 g _ d n g 1 g 2 g _ d n g 2 g 3 g _ d n g 3 g 4 g _ d n g 4 g 5 g _ d n g 5 g 6 g _ d n g 6 g 7 g _ d n g 7 g 8 g _ d n g 8 g 9 g _ d n g 9 g 0 1 g _ d n g 0 1 g 1 h _ d n g 1 h 2 h _ d n g 2 h 3 h _ d n g 3 h 4 h _ d n g 4 h 5 h _ d n g 5 h 6 h _ d n g 6 h 7 h _ d n g 7 h 8 h _ d n g 8 h 9 h _ d n g 9 h 0 1 h _ d n g 0 1 h 1 j _ d n g 1 j 2 j _ d n g 2 j 3 j _ d n g 3 j 4 j _ d n g 4 j 5 j _ d n g 5 j 6 j _ d n g 6 j 7 j _ d n g 7 j 8 j _ d n g 8 j 9 j _ d n g 9 j 0 1 j _ d n g 0 1 j 1 k _ d n g 1 k 2 k _ d n g 2 k 3 k _ d n g 3 k 4 k _ d n g 4 k 5 k _ d n g 5 k 6 k _ d n g 6 k 7 k _ d n g 7 k 8 k _ d n g 8 k 9 k _ d n g 9 k 0 1 k _ d n g 0 1 k 1 l _ d n g 1 l 2 l _ d n g 2 l 3 l _ d n g 3 l 4 l _ d n g 4 l 5 l _ d n g 5 l 6 l _ d n g 6 l 7 l _ d n g 7 l 8 l _ d n g 8 l 9 l _ d n g 9 l 0 1 l _ d n g 0 1 l 1 2 1 c f u 1 . 0 1 2 0 0 1 2 5 r 2 9 c f u 1 . 0 1 2 0 0 1 8 1 r 0 0 1 1 2 r 5 2 1 c f u 1 . 0 1 2
28 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 18. jtag and fpga programming 5 5 4 4 3 3 2 2 1 1 d d c c b b a a n t i n i c _ h s a l f s 1 _ q _ h s a l f s s m t o d t _ i c p j c c v s m t _ i c p s m t k c t i d t _ i c p i d t o d t k c t _ i c p v 3 . 3 _ c c v j c c v n t i n i n _ n e p s i k c t s m t i d t d _ h s a l f s q _ h s a l f s v 3 . 3 _ c c v k l c c c _ h s a l f s d _ h s a l f s n _ s _ h s a l f s n _ s _ h s a l f s n _ n e p s i n _ n e p s i k c t k c t i d t i d t k l c c n _ d l h _ 0 f s i p s i s v 3 . 3 _ c c v o d t v 3 . 3 _ c c v s e r x v 3 . 3 _ c c v v 3 . 3 _ c c v v 3 . 3 _ c c v 2 g f c 1 g f c 0 g f c v 3 . 3 _ c c v j c c v v 2 . 1 _ c c v k l c c v 3 . 3 _ c c v e n o d q _ h s a l f s 0 d i p s o d t v 3 . 3 _ c c v v 3 . 3 _ c c v v 3 . 3 _ c c v v 3 . 3 _ c c v v 3 . 3 _ c c v n m a r g o r p e n o d n t i n i n t i n i n r s g n i p s s c 6 2 y _ p t o d t v 3 . 3 _ c c v c _ h s a l f s d _ h s a l f s n _ s _ h s a l f s 1 _ q _ h s a l f s 2 _ q _ h s a l f s 2 _ q _ h s a l f s n _ w _ 0 f s i d t _ i c p o d t _ i c p k c t _ i c p s m t _ i c p i p s i s n i p s s c v 2 . 1 _ c c v v 3 . 3 _ c c v 0 d i p s n r s g 6 2 y _ p t e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c g n i m m a r g o r p a g p f d n a g a t j c 8 5 4 0 0 2 , 4 2 r e b m e v o n , y a d s e n d e w o d t n _ n e p s i e n o d i d t s m t k c t n t i n i e l b a c d a o l n w o dr e d a e h t u p n i t u p n i t u p n i t u p t u o t u p t u o t u p t u o t u p t u o r e d a e h e l b a c d a o l n w o d 0 1 x 1 r e d a e h e l b a c d a o l n w o d 5 x 2 1 ) t d p 4 h c t i w s e d i l s ( 4 w s f o s n o i t i s o p 2 ] 7 [ ] 7 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 4 [ ] 4 [ , ] 6 [ a r o p r o c r o t c u d n o c i m e s e c i t t a ln o i t ] 4 [ n w o d s s e r pd l o h d n a d l o h d n a p u s s e r p) n w o h s s a ( n o c s i h s a l f l a i r e s i p s o t d e t c e n s r e d a e h e l b a c d a o l n w o d8 p j d n a 6 p j s i h s a l f l a i r e s i p so t d e t c e n n o c p h s a l f 3 i p s r o f a g p fe d o m g n i m m a r g o r e d o m n o i t a r u g i f n o c 2 g f c 0 g f c 1 g f c g a t j p s i l a i r e s e v a l s l a i r e s r e t s a m h s a l f x i p s h s a l f 3 i p s l e l l a r a p e v a l s l e l l a r a p r e t s a m ) n o ( 0 ) f f o ( 1 x x x n o ) f f o ( 1 ) f f o ( 1 ) f f o ( 1 ) f f o ( 1 ) f f o ( 1 ) f f o ( 1 ) f f o ( 1 ) f f o ( 1 ) n o ( 0 ) n o ( 0 ) n o ( 0 ) n o ( 0 ) n o ( 0 ) n o ( 0 ) n o ( 0 ) n o ( 0 m a r g o r p n r s g ] 4 [ ] 4 [ ) 3 2 e ( m a r g o r p n e h w 7 p j t r o h sl a i r e s i p s g n i m e h t h g u o r h t h s a l f. " p i t f o s h s a l f l a i r e s i p s l a n o i t p o r e d n e v r o e z i s t n e r e f f i d r o f 1 5 c f u 1 . 0 1 2 9 u h s a l f l a i r e s i p s s / 1 q 2 w / 3 s s v 4 c c v 8 d l o h / 7 c 6 d 5 7 5 c f u 1 . 0 1 2 6 8 c f u 1 . 0 1 2 1 1 n r 3 8 0 x 1 4 7 s t c 3 3 1 2 3 4 8 7 6 5 5 0 1 c f u 1 . 0 1 2 2 8 c f u 1 . 0 1 2 7 1 1 c f u 1 . 0 1 2 7 2 c f u 1 . 0 1 2 1 7 r k 1 1 1 d n e e r g 3 0 6 0 d e l 7 2 1 c f u 1 . 0 1 2 2 3 1 c f u 1 . 0 1 2 6 1 1 c f u 1 . 0 1 2 4 6 c f u 1 . 0 1 2 8 3 c f u 1 . 0 1 2 9 2 c f u 1 . 0 1 2 6 p j 0 1 r e d a e h 1 2 3 4 5 6 7 8 9 0 1 9 8 c f u 1 . 0 1 2 6 3 c f u 1 . 0 1 2 4 w s a y e e 1 0 2 4 l t h c t i w s - e t d p 4 w s 4 u t 6 w m v - 0 8 p 5 2 m o r c i m t s h s a l f l a i r e s i p s s / 1 q 2 w / 3 s s v 4 c c v 8 d l o h / 7 c 6 d 5 1 0 1 c f u 1 . 0 1 2 2 7 r 0 0 1 8 2 1 c f u 1 . 0 1 2 9 d d e r 3 0 6 0 d e l 0 0 1 c f u 1 . 0 1 2 2 5 c f u 1 . 0 1 2 8 5 c f u 1 . 0 1 2 9 4 c f u 1 . 0 1 2 2 w s b 2 0 h 2 p q v e c i n o s a n a p n o t t u b h s u p w s 7 0 1 c f u 1 . 0 1 2 1 6 c f u 1 . 0 1 2 2 4 r 2 0 4 0 o e g a y % 1 k 0 1 7 9 c f u 1 . 0 1 2 5 9 c f u 1 . 0 1 2 9 1 1 c f u 1 . 0 1 2 7 2 r 0 2 2 8 p j 2 x 5 r e d a e h 1 2 3 4 5 6 7 8 9 0 1 3 3 1 c f u 1 . 0 1 2 0 1 d w o l l e y 3 0 6 0 d e l 5 1 1 c f u 1 . 0 1 2 8 0 1 c f u 1 . 0 1 2 7 3 c f u 1 . 0 1 2 k 0 1 6 6 r 8 2 c f u 1 . 0 1 2 0 3 j 3 n o c 1 2 3 4 1 1 c f u 1 . 0 1 2 5 3 c f u 1 . 0 1 2 5 2 r 0 2 2 4 3 c f u 1 . 0 1 2 0 5 1 c f u 0 . 1 1 2 1 3 c f u 1 . 0 1 2 k 0 1 8 6 r 3 0 1 c f u 1 . 0 1 2 3 5 c f u 1 . 0 1 2 5 5 c f u 1 . 0 1 2 0 5 c f u 1 . 0 1 2 9 5 c f u 1 . 0 1 2 6 0 1 c f u 1 . 0 1 2 6 2 r 0 2 2 8 2 r k 0 1 0 6 c f u 1 . 0 1 2 5 7 c f u 1 . 0 1 2 0 1 1 c f u 1 . 0 1 2 9 2 1 c f u 1 . 0 1 2 7 p j 2 r e d a e h 1 2 4 2 r k 0 1 8 1 1 c f u 1 . 0 1 2 6 2 c f u 1 . 0 1 2 3 2 r k 0 1 6 5 c f u 1 . 0 1 2 2 6 c f u 1 . 0 1 2 0 3 1 c f u 1 . 0 1 2 0 3 c f u 1 . 0 1 2 3 w s b 2 0 h 2 p q v e c i n o s a n a p n o t t u b h s u p w s ) 5 f o 5 ( 2 c e f l) 2 7 6 a g b p f ( e 0 e 3 u 2 7 6 - c e 0 2 c e f l c c v 8 h c c v 9 h c c v 0 1 h c c v 1 1 h c c v 6 1 h c c v 7 1 h c c v 8 1 h c c v 9 1 h c c v 9 j c c v 8 1 j c c v 8 k c c v 9 1 k c c v 8 l c c v 9 1 l c c v 9 1 m c c v 7 n c c v 7 r c c v 0 2 r c c v 9 1 t c c v 8 u c c v 9 1 u c c v 8 v c c v 9 v c c v 8 1 v c c v 8 w c c v 9 w c c v 0 1 w c c v 1 1 w c c v 6 1 w c c v 7 1 w c c v 8 1 w c c v 9 1 w k c t 7 u s m t 5 v o d t 3 v i d t 4 v j c c v 6 u s e r x 3 n 0 g f c 3 2 v 1 g f c 1 2 v 2 g f c 4 2 v n m a r g o r p 2 2 v k l c c 0 2 v e n o d 0 2 u n t i n i 5 2 v d n g 0 1 k x u a c c v 3 1 g x u a c c v 7 h x u a c c v 0 2 h x u a c c v 8 j x u a c c v 9 1 j x u a c c v 7 k x u a c c v 0 2 l x u a c c v 7 m x u a c c v 0 2 m x u a c c v 0 2 n x u a c c v 7 p x u a c c v 0 2 p x u a c c v 7 t x u a c c v 8 t x u a c c v 0 2 t x u a c c v 7 v x u a c c v 9 1 v x u a c c v 0 2 w x u a c c v 7 y x u a c c v 3 1 y d n g 1 1 k d n g 2 1 k d n g 3 1 k d n g 4 1 k d n g 5 1 k d n g 6 1 k d n g 0 1 l d n g 1 1 l d n g 2 1 l d n g 3 1 l d n g 4 1 l d n g 5 1 l d n g 6 1 l d n g 7 1 l d n g 0 1 m d n g 1 1 m d n g 2 1 m d n g 3 1 m d n g 4 1 m d n g 5 1 m d n g 6 1 m d n g 7 1 m d n g 0 1 n d n g 1 1 n d n g 2 1 n d n g 3 1 n d n g 4 1 n d n g 5 1 n d n g 6 1 n d n g 7 1 n d n g 0 1 p d n g 1 1 p d n g 2 1 p d n g 3 1 p d n g 4 1 p d n g 5 1 p d n g 6 1 p d n g 7 1 p d n g 0 1 r d n g 1 1 r d n g 2 1 r d n g 3 1 r d n g 4 1 r d n g 5 1 r d n g 6 1 r d n g 7 1 r d n g 0 1 t d n g 1 1 t d n g 2 1 t d n g 3 1 t d n g 4 1 t d n g 5 1 t d n g 6 1 t d n g 7 1 t d n g 0 1 u d n g 1 1 u d n g 2 1 u d n g 3 1 u d n g 4 1 u d n g 5 1 u d n g 6 1 u d n g 7 1 u 5 w s t s m 3 - 4 9 1 s t c 3 - p i d w s 1 2 3 6 5 4 k 0 1 7 6 r 4 0 1 c f u 1 . 0 1 2 9 3 c f u 1 . 0 1 2 3 1 1 c f u 1 . 0 1 2 2 2 r k 0 1
29 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 19. prototyping support 5 5 4 4 3 3 2 2 1 1 d d c c b b a a 6 w _ a m s 2 n _ a m s 2 w _ p t 1 n _ a m s 1 b _ p t 4 n i p _ 5 4 j r 3 n i p _ 5 4 j r 2 n i p _ 5 4 j r 1 n i p _ 5 4 j r 1 n i p _ 5 4 j r 6 n i p _ 5 4 j r 5 n i p _ 5 4 j r 8 n i p _ 5 4 j r 7 n i p _ 5 4 j r 1 y _ a m s 1 c _ p t 1 d _ p t 1 e _ p t 1 f _ p t 1 g _ p t 1 h _ p t 1 j _ p t 1 k _ p t 1 l _ p t 1 m _ p t 1 p _ p t 1 r _ p t 1 t _ p t 1 u _ p t 1 v _ p t 1 e _ p t 1 d _ p t 1 c _ p t 1 b _ p t 1 v _ p t 1 u _ p t 1 t _ p t 1 l _ p t 1 l _ p t 1 j _ p t 2 d _ p t 2 e _ p t 2 f _ p t 2 g _ p t 2 k _ p t 2 l _ p t 2 m _ p t 2 p _ p t 2 r _ p t 2 t _ p t 2 u _ p t 2 v _ p t 3 e _ p t 3 f _ p t 3 g _ p t 3 k _ p t 3 l _ p t 3 m _ p t 3 p _ p t 3 r _ p t 3 t _ p t 3 u _ p t 4 e _ p t 4 g _ p t 4 h _ p t 4 j _ p t 4 k _ p t 4 l _ p t 4 m _ p t 4 n _ p t 4 p _ p t 4 r _ p t 4 t _ p t 4 u _ p t 4 c a _ p t 4 b a _ p t 5 j _ p t 5 k _ p t 5 l _ p t 5 m _ p t 5 n _ p t 5 p _ p t 5 r _ p t 5 t _ p t 5 u _ p t 6 j _ p t 6 k _ p t 6 l _ p t 6 m _ p t 6 n _ p t 6 p _ p t 6 r _ p t 6 t _ p t 7 l _ p t 3 e _ p t 4 e _ p t 1 p _ p t 3 f _ p t 3 g _ p t 2 d _ p t 2 e _ p t 2 f _ p t 2 g _ p t 6 g _ p t 6 g _ p t 4 g _ p t 4 h _ p t 4 j _ p t 5 j _ p t 4 k _ p t 5 k _ p t 6 j _ p t 6 k _ p t 2 p _ p t 6 l _ p t 7 l _ p t 4 n _ p t 5 n _ p t 2 r _ p t 4 p _ p t 3 p _ p t 5 m _ p t 6 m _ p t 2 t _ p t 4 r _ p t 3 r _ p t 6 n _ p t 5 p _ p t 6 p _ p t 5 r _ p t 2 u _ p t 3 t _ p t 4 t _ p t 6 r _ p t 5 t _ p t 6 t _ p t 5 u _ p t 3 u _ p t 4 u _ p t 2 v _ p t 4 c a _ p t 4 b a _ p t 2 k _ p t 3 k _ p t 3 l _ p t 2 l _ p t 2 m _ p t 3 m _ p t 4 m _ p t 4 l _ p t 5 l _ p t 1 r _ p t 1 p _ p t 1 u _ p t 1 v _ p t 1 r _ p t 1 t _ p t 1 k _ p t 1 k _ p t 1 m _ p t 1 m _ p t v 5 . 2 _ c c v 3 n i p _ 5 4 j r 5 n i p _ 5 4 j r 7 n i p _ 5 4 j r 2 n i p _ 5 4 j r 4 n i p _ 5 4 j r 6 n i p _ 5 4 j r 8 n i p _ 5 4 j r 2 y _ a m s 6 v _ a m s v 3 . 3 _ c c v v 5 . 2 _ c c v 1 g _ p t 1 h _ p t 1 f _ p t v 5 . 2 _ c c v k l c _ i c p 2 w _ p t k l c l l p _ c s o k l c p _ c s o 7 _ o i c c v 6 _ o i c c v 2 e a _ p t 2 f a _ p t 3 b _ p t 3 e a _ p t 3 f a _ p t 4 b _ p t 4 c _ p t 4 d _ p t 4 a _ p t 4 d a _ p t 5 b _ p t 5 c a _ p t 5 c _ p t 5 a _ p t 5 d a _ p t 5 e a _ p t 5 f a _ p t 6 b _ p t 6 c a _ p t 6 c _ p t 6 d _ p t 6 e _ p t 6 a a _ p t 6 b a _ p t 6 a _ p t 6 d a _ p t 6 e a _ p t 6 f a _ p t 7 b _ p t 7 c a _ p t 7 c _ p t 7 d _ p t 7 e _ p t 7 f _ p t 7 g _ p t 7 a a _ p t 7 b a _ p t 7 a _ p t 7 d a _ p t 7 e a _ p t 7 f a _ p t 8 b _ p t 8 c a _ p t 8 c _ p t 8 d _ p t 8 e _ p t 8 f _ p t 8 g _ p t 8 y _ p t 8 a a _ p t 8 b a _ p t 8 a _ p t 8 d a _ p t 8 e a _ p t 8 f a _ p t 9 c a _ p t 9 d _ p t 9 e _ p t 9 f _ p t 9 g _ p t 9 y _ p t 9 a a _ p t 9 b a _ p t 9 d a _ p t 9 e a _ p t 9 f a _ p t 0 1 f a _ p t 0 1 c a _ p t 0 1 y _ p t 0 1 a a _ p t 0 1 b a _ p t 1 1 c a _ p t 1 1 y _ p t 1 1 a a _ p t 1 1 b a _ p t 2 1 c a _ p t 0 1 d a _ p t 0 1 e a _ p t 1 1 f a _ p t 1 1 d a _ p t 1 1 e a _ p t 2 1 f a _ p t 2 1 d a _ p t 2 1 e a _ p t v 5 . 2 _ c c v v 3 . 3 _ c c v k l c _ i c p k l c p _ c s o e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c t r o p p u s g n i p y t o t o r p c 8 6 4 0 0 2 , 4 2 r e b m e v o n , y a d s e n d e w , ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 3 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 2 [ ] 7 [ ] 7 [ ] 7 [ ] 7 [ , ] 5 [ a r o p r o c r o t c u d n o c i m e s e c i t t a ln o i t n o ) 2 n ( p ) 1 n ( n ) 1 y ( p ) 2 y ( n ) 6 v ( p ) 6 w ( n ) 6 f ( 1 c s o ) 1 e ( d e l ) 1 d ( d e l ) 1 c ( d e l ) 1 b ( d e l ) 1 g ( d e l ) 1 h ( d e l ) 1 j ( d e l ) 1 a a ( ) 4 y ( ) 4 w ( ) 2 b a ( ) 1 b a ( ) 3 y ( ) 3 w ( ) 1 c a ( 1 ) 1 k ( 2 ) 1 l ( 3 ) 1 m ( 4 ) 1 p ( 5 ) 1 r ( 6 ) 1 t ( 7 ) 1 u ( 8 ) 1 v ( ) 1 f ( d e l ] 2 [ a ( 2 c s o) 4 1 f r o t a l l i c s ot e k c o s ) d e l l a t s n i c s o z h m 3 3 . 3 3 ( ] 2 [ b 1 p t n i p a g p f 2 d 2 d 2 e 2 e 2 f 2 f 2 g 2 g 2 k 2 k 2 l 2 l 2 m 2 m 2 p 2 p 2 r 2 r 2 t 2 t 2 u 2 u 2 v 2 v 2 e a 2 e a 2 f a 2 f a 2 w 2 w 3 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 1 w s t s m 8 - 4 9 1 s t c 8 - p i d w s 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 0 4 c f u 1 . 0 1 2 1 j 5 4 - j r 1 2 3 4 5 6 7 8 f 1 p t n i p a g p f 6 a 6 a 6 b 6 b 6 c 6 c 6 d 6 d 6 e 6 e 6 g 6 g 6 j 6 j 6 k 6 k 6 l 6 l 6 m 6 m 6 n 6 n 6 p 6 p 6 r 6 r 6 t 6 t 6 a a 6 a a 6 b a 6 b a 6 c a 6 c a 6 d a 6 d a 6 e a 6 e a 6 f a 6 f a 8 3 r k 0 1 2 2 6 r 0 7 c f u 1 . 0 1 2 6 k n a b 7 k n a b 2 c e f l) 2 7 6 a g b p f ( e 0 ) 5 f o 1 ( a 3 u 2 7 6 - c e 0 2 c e f l 7 _ 2 f e r v / a 2 l p 3 e 7 _ 1 f e r v / b 2 l p 4 e a 3 l p 1 b b 3 l p 1 c a 4 l p 3 f b 4 l p 3 g a 5 l p 2 d b 5 l p 2 e 6 s q d l / a 6 l p 1 d b 6 l p 1 e a 7 l p 2 f b 7 l p 2 g a _ n i _ t l l p _ 0 m u l / a 8 l p 6 f a _ n i _ c l l p _ 0 m u l / b 8 l p 6 g a _ b f _ t l l p _ 0 m u l / a 9 l p 4 h a _ b f _ c l l p _ 0 m u l / b 9 l p 4 g a 1 1 l p 4 j b 1 1 l p 5 j a 2 1 l p 4 k b 2 1 l p 5 k a 3 1 l p 6 j b 3 1 l p 6 k a 4 1 l p 1 f b 4 1 l p 1 g a 5 1 l p 1 h b 5 1 l p 1 j a 6 1 l p 2 k b 6 1 l p 1 k a 7 1 l p 3 k b 7 1 l p 3 l a 8 1 l p 2 l b 8 1 l p 1 l 9 1 s q d l / a 9 1 l p 3 m b 9 1 l p 4 m a 0 2 l p 1 m b 0 2 l p 2 m a 1 2 l p 4 l b 1 2 l p 5 l 0 _ 7 t k l c p / a 2 2 l p 2 n 0 _ 7 c k l c p / b 2 2 l p 1 n 7 o c c v 9 k 7 o c c v 9 l 7 o c c v 8 m 7 o c c v 8 n 7 o c c v 9 n 7 o c c v 9 m a 4 2 l p 1 p b 4 2 l p 2 p a 5 2 l p 7 l b 5 2 l p 6 l a 6 2 l p 4 n b 6 2 l p 5 n a 7 2 l p 1 r b 7 2 l p 2 r a 8 2 l p / 8 2 s q d l 4 p b 8 2 l p 3 p a 9 2 l p 5 m b 9 2 l p 6 m a 0 3 l p 1 t b 0 3 l p 2 t a 1 3 l p 4 r b 1 3 l p 3 r a 2 3 l p 6 n b 2 3 l p 5 p a 3 3 l p 6 p b 3 3 l p 5 r a 4 3 l p 1 u b 4 3 l p 2 u a 5 3 l p 3 t b 5 3 l p 4 t a 6 3 l p / 6 3 s q d l 6 r b 6 3 l p 5 t a 7 3 l p 6 t b 7 3 l p 5 u a 8 3 l p 3 u b 8 3 l p 4 u a 9 3 l p 1 v b 9 3 l p 2 v a 1 4 l p / a _ n i _ t l l p _ 0 m l l 1 w b 1 4 l p / a _ n i _ c l l p _ 0 m l l 2 w a 2 4 l p / a _ b f _ t l l p _ 0 m l l 6 v b 2 4 l p / a _ b f _ c l l p _ 0 m l l 6 w a 3 4 l p 1 y b 3 4 l p 2 y a 4 4 l p 3 w b 4 4 l p 4 w a 5 4 l p / 5 4 s q d l 1 a a b 5 4 l p 1 b a a 6 4 l p 4 y b 6 4 l p 3 y a 7 4 l p 1 c a b 7 4 l p 2 b a a 8 4 l p / 6 _ 1 f e r v 4 b a b 8 4 l p / 6 _ 2 f e r v 4 c a 6 o c c v 8 p 6 o c c v 9 p 6 o c c v 8 r 6 o c c v 9 r 6 o c c v 9 t 6 o c c v 9 u 4 3 r k 0 1 4 d n e e r g 3 0 6 0 d e l 6 4 c f u 1 . 0 1 2 5 d n e e r g 3 0 6 0 d e l 2 2 3 r 7 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 k 1 p t n i p a g p f 1 1 y 1 1 y 1 1 a a 1 1 a a 1 1 b a 1 1 b a 1 1 c a 1 1 c a 1 1 d a 1 1 d a 1 1 e a 1 1 e a 1 1 f a 1 1 f a c 1 p t n i p a g p f 3 b 3 b 3 e 3 e 3 f 3 f 3 g 3 g 3 k 3 k 3 l 3 l 3 m 3 m 3 p 3 p 3 r 3 r 3 t 3 t 3 u 3 u 3 e a 3 e a 3 f a 3 f a 2 7 c f u 1 . 0 1 2 e 1 p t n i p a g p f 5 a 5 a 5 b 5 b 5 c 5 c 5 j 5 j 5 k 5 k 5 l 5 l 5 m 5 m 5 n 5 n 5 p 5 p 5 r 5 r 5 t 5 t 5 u 5 u 5 c a 5 c a 5 d a 5 d a 5 e a 5 e a 5 f a 5 f a 2 2 4 r 9 3 r k 0 1 2 2 7 r 5 3 r k 0 1 3 d n e e r g 3 0 6 0 d e l 8 4 1 c 5 0 8 0 f u 0 1 1 2 5 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 1 7 c f u 1 . 0 1 2 2 4 c f u 1 . 0 1 2 d 1 p t n i p a g p f 4 a 4 a 4 b 4 b 4 c 4 c 4 d 4 d 4 e 4 e 4 g 4 g 4 h 4 h 4 j 4 j 4 k 4 k 4 l 4 l 4 m 4 m 4 n 4 n 4 p 4 p 4 r 4 r 4 t 4 t 4 u 4 u 4 b a 4 b a 4 c a 4 c a 4 d a 4 d a 1 y 2 x 8 - c o s p i d 1 2 3 4 5 6 7 8 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 5 4 c f u 1 . 0 1 2 2 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 j 1 p t n i p a g p f 0 1 y 0 1 y 0 1 a a 0 1 a a 0 1 b a 0 1 b a 0 1 c a 0 1 c a 0 1 d a 0 1 d a 0 1 e a 0 1 e a 0 1 f a 0 1 f a 7 d n e e r g 3 0 6 0 d e l 4 4 c f u 1 . 0 1 2 0 4 r k 0 1 8 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 1 p j 2 x 4 r e d a e h 1 2 3 4 5 6 7 8 g 1 p t n i p a g p f 7 a 7 a 7 b 7 b 7 c 7 c 7 d 7 d 7 e 7 e 7 f 7 f 7 g 7 g 7 a a 7 a a 7 b a 7 b a 7 c a 7 c a 7 d a 7 d a 7 e a 7 e a 7 f a 7 f a 7 l 7 l 2 2 8 r 6 3 r k 0 1 a 1 p t n i p a g p f 1 b 1 b 1 c 1 c 1 d 1 d 1 e 1 e 1 f 1 f 1 g 1 g 1 h 1 h 1 j 1 j 1 k 1 k 1 l 1 l 1 m 1 m 1 p 1 p 1 r 1 r 1 t 1 t 1 u 1 u 1 v 1 v 2 d n e e r g 3 0 6 0 d e l 4 j 5 0 0 - 3 1 1 1 - 0 5 6 9 p e a r o t c e n n o c a m s s 1 7 4 1 c 5 0 8 0 f u 0 1 1 2 3 4 c f u 1 . 0 1 2 l 1 p t n i p a g p f 2 1 c a 2 1 c a 2 1 d a 2 1 d a 2 1 e a 2 1 e a 2 1 f a 2 1 f a 2 2 1 r 1 4 c f u 1 . 0 1 2 i 1 p t n i p a g p f 9 d 9 d 9 e 9 e 9 f 9 f 9 g 9 g 9 y 9 y 9 a a 9 a a 9 b a 9 b a 9 c a 9 c a 9 d a 9 d a 9 e a 9 e a 9 f a 9 f a h 1 p t n i p a g p f 8 a 8 a 8 b 8 b 8 c 8 c 8 d 8 d 8 e 8 e 8 f 8 f 8 g 8 g 8 y 8 y 8 a a 8 a a 8 b a 8 b a 8 c a 8 c a 8 d a 8 d a 8 e a 8 e a 8 f a 8 f a 2 2 5 r 7 3 r k 0 1 1 d n e e r g 3 0 6 0 d e l 7 4 c f u 1 . 0 1 2 3 3 r k 0 1 8 4 c f u 1 . 0 1 2 8 d n e e r g 3 0 6 0 d e l 6 d n e e r g 3 0 6 0 d e l 2 2 2 r
30 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 20. power 5 5 4 4 3 3 2 2 1 1 d d c c b b a a p w r_3.3 v gate_1.2 p w r_1.2 v v cc_1.2 v v ccio_0 v ccio_1 v ccio_2 v ccio_3 v ccio_4 v ccio_5 v ccio_6 v ccio_7 v ccio_0 v ccio_1 v ccio_2 v ccio_3 v ccio_4 v ccio_5 v ccio_6 v ccio_7 v ccio_0 v ccio_1 v ccio_2 v ccio_3 v ccio_4 v ccio_5 v ccio_6 v ccio_7 v ccio_0 v ccio_1 v ccio_2 v ccio_3 v ccio_4 v ccio_5 v ccio_6 v ccio_7 v cc_2.5 v v cc_1.2 v v cc_2.5 v drai n _2.5 drai n _1.2 v cc_i n v cc_i n pci_3.3 v p w r_adj v cc_i n v cc_i n v cc_i n p w r_2.5 v gate_2.5 drai n _2.5 v cc_i n gate_1.2 drai n _1.2 v cc_i n v cc_3.3 v pci_3.3 v v cc_3.3 v gate_2.5 v cc_adj v cc_adj v cc_1.2 v v ccio_0 v ccio_1 v ccio_2 v ccio_3 v ccio_4 v ccio_5 v ccio_6 v ccio_7 v cc_2.5 v pci_3.3 v v cc_3.3 v pci_g n d_57 title size doc u ment nu m b er e v date heet of c po w er c 7 8 monday, fe b r u ary 07, 2005 [5] [6] [2] [2] [3], [3] [3] [4] [4] [2] [2] [6] [6] [6] [5], lattice semiconductor corporation another p-channel mosfet option in sot23 package another p-channel mosfet option in sot23 package +5vdc vccio voltage selection gnd pins for signal probing 2.5v / 2.6v voltage selection r29 10k q4 si5475dc v ishay siliconix 1206- 8 j20 ba n a n a jack s 1 jp4 header 8 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r69 51 j17 ba n a n a jack s 1 r64 51k 1 % yageo 0402 f3 1.5a fuse littelf u se 15401.5 1 2 q2 si2323ds v ishay siliconix sot23 g d s d14 1 n 5 8 20 j26 co n 1 1 c139 10 u f 0 8 05 1 2 d13 1 n 5 8 20 r62 39k 1 % yageo 0402 f2 3a fuse littelf u se 154003 1 2 c9 4.7pf 1 2 u7 tps64203d v b /e n 1 g n d 2 fb 3 ise n se 4 v i n 5 s w 6 d12 1 n 5 8 20 c15 10 u f size c 1 2 r65 30.1k 1 % yageo 0402 + c12 2.2 u f size b jp2 header 8 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d16 b320a diodes inc. q1 si2323ds v ishay siliconix sot23 g d s f4 1.5a fuse littelf u se 15401.5 1 2 r70 51 r75 36k 1 % yageo 0402 j27 co n 1 1 c6 100 u f size d 1 2 c14 10 u f size c 1 2 c140 10 u f 0 8 05 1 2 j32 co n 3 1 2 3 u5 tps7 8 601ktt v i n 2 e n 1 g n d 3 v out 4 fb 5 r63 42.2k 1 % yageo 0402 j2 8 co n 1 1 j24 co n 1 1 l1 6.2 u h s u mida cdrh6d3 8 -6r2 1 2 c13 4.7 u f size b 1 2 jp5 header 8 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 u6 tps7 8 601ktt v i n 2 e n 1 g n d 3 v out 4 fb 5 j22 p w r jack s w itchcraft rapc722 3 2 1 c137 10 u f 0 8 05 1 2 r30 30.1k 1 % yageo 0402 j29 co n 1 1 q3 si5475dc v ishay siliconix 1206- 8 j16 ba n a n a jack s 1 + c10 2.2 u f size b u 8 tps64203d v b /e n 1 g n d 2 fb 3 ise n se 4 v i n 5 s w 6 c5 100 u f size d 1 2 j19 ba n a n a jack s 1 jp3 header 8 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 l2 6.2 u h s u mida cdrh6d3 8 -6r2 1 2 c11 4.7 u f size b 1 2 j1 8 ba n a n a jack s 1 c7 1 u f size a 1 2 r31 10k j21 ba n a n a jack s 1 r32 50k pot m u rata p v g5h503a01 1 3 2 j25 co n 1 1 c13 8 10 u f 0 8 05 1 2 f1 3a fuse littelf u se 154003 1 2 d15 b320a diodes inc. c 8 1 u f size a 1 2
31 latticeec advanced evaluation board ? lattice semiconductor revision c user? guide figure 21. mechanical drawing 5 5 4 4 3 3 2 2 1 1 d d c c b b a a e l t i t v e r r e b m u n t n e m u c o d e z i s t e e h s : e t a d f o c g n i w a r d l a c i n a h c e m c 8 8 5 0 0 2 , 1 2 y r a u n a j , y a d i r f a r o p r o c r o t c u d n o c i m e s e c i t t a ln o i t

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